| Low Subthreshold Swing and High Mobility Amorphous Indium–Gallium–Zinc-Oxide Thin-Film Transistor With Thin HfO2 Gate Dielectric and Excellent Uniformity S Samanta, U Chand, S Xu, K Han, Y Wu, C Wang, A Kumar, H Velluri, ... IEEE Electron Device Letters 41 (6), 856-859, 2020 | 53 | 2020 |
| First Demonstration of BEOL-Compatible Ferroelectric TCAM Featuring a-IGZO Fe-TFTs with Large Memory Window of 2.9 V, Scaled Channel Length of 40 nm, and High Endurance of 10 8 … C Sun, K Han, S Samanta, Q Kong, J Zhang, H Xu, X Wang, A Kumar, ... 2021 Symposium on VLSI Technology, 1-2, 2021 | 39 | 2021 |
| The first GeSn FinFET on a novel GeSnOI substrate achieving lowest S of 79 mV/decade and record high Gm, int of 807 μS/μm for GeSn P-FETs D Lei, KH Lee, S Bao, W Wang, S Masudy-Panah, S Yadav, A Kumar, ... 2017 Symposium on VLSI Technology, T198-T199, 2017 | 31 | 2017 |
| Germanium-Tin (GeSn) P-Channel Fin Field-Effect Transistor Fabricated on a Novel GeSn-on-Insulator Substrate D Lei, KH Lee, YC Huang, W Wang, S Masudy-Panah, S Yadav, A Kumar, ... IEEE Transactions on Electron Devices 65 (9), 3754-3761, 2018 | 30 | 2018 |
| Ge0.95Sn0.05 Gate-All-Around p-Channel Metal-Oxide-Semiconductor Field-Effect Transistors with Sub-3 nm Nanowire Width Y Kang, S Xu, K Han, EYJ Kong, Z Song, S Luo, A Kumar, C Wang, W Fan, ... Nano Letters 21 (13), 5555-5563, 2021 | 28 | 2021 |
| Temperature-Dependent Operation of InGaZnO Ferroelectric Thin-Film Transistors With a Metal-Ferroelectric-Metal-Insulator-Semiconductor Structure C Sun, Z Zheng, K Han, S Samanta, J Zhou, Q Kong, J Zhang, H Xu, ... IEEE Electron Device Letters 42 (12), 1786-1789, 2021 | 25 | 2021 |
| Amorphous InGaZnO Thin-Film Transistors With Sub-10-nm Channel Thickness and Ultrascaled Channel Length S Samanta, K Han, C Sun, C Wang, A Kumar, AVY Thean, X Gong IEEE Transactions on Electron Devices 68 (3), 1050-1056, 2021 | 23 | 2021 |
| SiGe and III-V materials and devices: New HEMT and LED elements in 0.18-micron CMOS process and design EA Fitzgerald, KE Lee, SF Yoon, SJ Chua, CS Tan, GI Ng, X Zhou, ... ECS Transactions 75 (8), 439, 2016 | 20 | 2016 |
| First monolithic integration of Ge P-FETs and InAs N-FETs on silicon substrate: Sub-120 nm III-V buffer, sub-5 nm ultra-thin body, common raised S/D, and gate stack modules S Yadav, KH Tan, KH Goh, S Subramanian, KL Low, N Chen, B Jia, ... 2015 IEEE International Electron Devices Meeting (IEDM), 2.3. 1-2.3. 4, 2015 | 20 | 2015 |
| Highly scaled InGaZnO ferroelectric field-effect transistors and ternary content-addressable memory C Sun, K Han, S Samanta, Q Kong, J Zhang, H Xu, X Wang, A Kumar, ... IEEE Transactions on Electron Devices 69 (9), 5262-5269, 2022 | 17 | 2022 |
| Nanoscale metal-InGaAs contacts with ultra-low specific contact resistivity: Improved interfacial quality and extraction methodology S Masudy-Panah, Y Wu, D Lei, A Kumar, YC Yeo, X Gong Journal of Applied Physics 123 (2), 2018 | 17 | 2018 |
| Heteroepitaxial growth of In0. 30Ga0. 70As high-electron mobility transistor on 200 mm silicon substrate using metamorphic graded buffer D Kohen, XS Nguyen, S Yadav, A Kumar, RI Made, C Heidelberger, ... AIP Advances 6 (8), 2016 | 17 | 2016 |
| Monolithic integration of InAs quantum-well n-MOSFETs and ultrathin body Ge p-MOSFETs on a Si substrate S Yadav, KH Tan, A Kumar, KH Goh, G Liang, SF Yoon, X Gong, YC Yeo IEEE Transactions on Electron Devices 64 (2), 353-360, 2016 | 13 | 2016 |
| Gate-all-around CMOS (InAs n-FET and GaSb p-FET) based on vertically-stacked nanowires on a Si platform, enabled by extremely-thin buffer layer technology and common gate stack … KH Goh, KH Tan, S Yadav, SF Yoon, G Liang, X Gong, YC Yeo 2015 IEEE International Electron Devices Meeting (IEDM), 15.4. 1-15.4. 4, 2015 | 13 | 2015 |
| Extremely Scaled Bottom Gate a-IGZO Transistors Using a Novel Patterning Technique Achieving Record High G m of 479.5 μS/μm (V DS of 1 V) and f T of 18.3 GHz (V DS of 3 V) C Wang, A Kumar, K Han, C Sun, H Xu, J Zhang, Y Kang, Q Kong, ... 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022 | 11 | 2022 |
| First Demonstration of Complementary FinFETs and Tunneling FinFETs Co-Integrated on a 200 mm GeSnOI Substrate: A Pathway towards Future Hybrid Nano-electronics Systems K Han, Y Wu, YC Huang, S Xu, A Kumar, E Kong, Y Kang, J Zhang, ... 2019 Symposium on VLSI Technology, T182-T183, 2019 | 10 | 2019 |
| GeSn p-FinFETs with Sub-10 nm Fin Width Realized on a 200 mm GeSnOI Substrate: Lowest SS of 63 mV/decade, Highest Gm,intof 900 µS/µm, and High-Field µeffof 275 cm … D Lei, K Han, KH Lee, YC Huang, W Wang, S Yadav, A Kumar, Y Wu, ... 2018 IEEE Symposium on VLSI Technology, 197-198, 2018 | 10 | 2018 |
| High mobility In0.30Ga0.70As MOSHEMTs on low threading dislocation density 200 mm Si substrates: A technology enabler towards heterogeneous integration of … S Yadav, A Kumar, XS Nguyen, KH Lee, Z Liu, W Xing, S Masudy-Panah, ... 2017 IEEE International Electron Devices Meeting (IEDM), 17.4. 1-17.4. 4, 2017 | 8 | 2017 |
| Back-End-of-Line Compatible Fully Depleted CMOS Inverters Employing Ge p-FETs and α-InGaZnO n-FETs Y Kang, K Han, A Kumar, C Wang, C Sun, Z Zhou, J Zhou, X Gong IEEE Electron Device Letters 42 (10), 1488-1491, 2021 | 7 | 2021 |
| MOCVD growth of high quality InGaAs HEMT layers on large scale Si wafers for heterogeneous integration with Si CMOS XS Nguyen, S Yadav, KH Lee, D Kohen, A Kumar, RI Made, KEK Lee, ... IEEE Transactions on Semiconductor Manufacturing 30 (4), 456-461, 2017 | 7 | 2017 |
Xiao GongNational University of SingaporeVerifierad e-postadress på nus.edu.sg
