| Sensitivity analysis of a novel negative capacitance FinFET for label-free biosensing A Dixit, DP Samajdar, V Chauhan IEEE Transactions on Electron Devices 68 (10), 5204-5210, 2021 | 26 | 2021 |
| Recent advances in negative capacitance FinFETs for low power applications: a review V Chauhan, DP Samajdar IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control 68 …, 2021 | 23 | 2021 |
| A novel negative capacitance FinFET with ferroelectric spacer: proposal and investigation V Chauhan, DP Samajdar, N Bagga, A Dixit IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control 68 …, 2021 | 20 | 2021 |
| Exploration and Device Optimization of Dielectric–Ferroelectric Sidewall Spacer in Negative Capacitance FinFET V Chauhan, DP Samajdar, N Bagga IEEE Transactions on Electron Devices 69 (8), 4717-4724, 2022 | 7 | 2022 |
| Performance Comparison of III–V and Silicon FinFETs for Ultra-Low Power VLSI Applications A Dixit, DP Samajdar, V Chauhan, N Bagga Microelectronics, Circuits and Systems, 93-100, 2021 | 5 | 2021 |
| Demonstration of Improved Short Channel Performance Metrics for Ferroelectric Concentric Negative Capacitance FinFET V Chauhan, DP Samajdar, N Bagga Silicon-Springer 38, 1-7, 2022 | 3 | 2022 |
| Estimation of performance degradation due to interface traps in the gate and spacer stack of NC-FinFET V Chauhan, DP Samajdar Semiconductor Science and Technology 38 (4), 045012, 2023 | 2 | 2023 |
| Buried interfacial gate oxide for tri-gate negative-capacitance fin field-effect transistors: approach and investigation V Chauhan, DP Samajdar Journal of Physics D: Applied Physics 56 (40), 405111, 2023 | 1 | 2023 |
| Quasi-analytical model of surface potential and drain current for trigate negative capacitance FinFET: a superposition approach V Chauhan, DP Samajdar, N Bagga Semiconductor Science and Technology 37 (8), 085018, 2022 | 1 | 2022 |
| Impact of Buried Gate Oxide on the Electrical Performance of Negative Capacitance FinFETs: Design Perspectives V Chauhan, DP Samajdar Silicon, 1-8, 2024 | | 2024 |
| A Tri-Gate Negative Capacitance FinFET device with Buried Interfacial Oxide layer and its Fabrication Method V Chauhan, DP Samajdar IN Patent IND 441,737, 2023 | | 2023 |
| Performance Evaluation of Buried Gate Oxide based Negative Capacitance FinFETs V Chauhan, DP Samajdar 2023 IEEE Devices for Integrated Circuit (DevIC), 465-469, 2023 | | 2023 |
| Demonstration of High-Permittivity Sidewall Spacer in Negative Capacitance FinFET V Chauhan, DP Samajdar, N Bagga Tailored Functional Materials: Select Proceedings of MMETFP 2021, 495-502, 2022 | | 2022 |
| Sub-1 V Ultra-Low Power CMOS Operational Transconductance Amplifier V Chauhan 6th International Conference on ‘Microelectronics, Circuits and Systems …, 2019 | | 2019 |
