Hans-Joachim Wunderlich
Hans-Joachim Wunderlich
Professor of Computer Science, University of Stuttgart
Verifierad e-postadress på informatik.uni-stuttgart.de - Startsida
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Minimized power consumption for scan-based BIST
S Gerstendörfer, HJ Wunderlich
Journal of Electronic Testing 16 (3), 203-212, 2000
4932000
Bit-flipping BIST
HJ Wunderlich, G Kiefer
Proceedings of International Conference on Computer Aided Design, 337-343, 1996
2891996
Multiple distributions for biased random test patterns
HJ Wunderlich
IEEE transactions on computer-aided design of integrated circuits and …, 1990
2811990
Power-aware design-for-test
HJ Wunderlich, CG Zoellin
Power-Aware Testing and Test Strategies for Low Power Devices, 117-146, 2010
264*2010
Pattern generation for a deterministic BIST scheme
S Hellebrand, B Reeb, S Tarnick, HJ Wunderlich
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD …, 1995
1881995
A modified clock scheme for a low power BIST test pattern generator
P Girard, L Guiller, C Landrault, S Pravossoudovitch, HJ Wunderlich
Proceedings 19th IEEE VLSI Test Symposium. VTS 2001, 306-311, 2001
1862001
A mixed mode BIST scheme based on reseeding of folding counters
S Hellebrand, HG Liang, HJ Wunderlich
Journal of Electronic Testing 17 (3), 341-349, 2001
1822001
Low power serial built-in self-test
A Hertwig, HJ Wunderlich
Proceedings of IEEE European Test Workshop, 1998, 1998
1701998
Two-dimensional test data compression for scan-based deterministic BIST
HG Liang, S Hellebrand, HJ Wunderlich
Journal of Electronic Testing 18 (2), 159-170, 2002
1502002
PROTEST: A tool for probabilistic testability analysis
HJ Wunderlich
22nd ACM/IEEE Design Automation Conference, 204-211, 1985
1401985
Adaptive debug and diagnosis without fault dictionaries
S Holst, HJ Wunderlich
Journal of Electronic Testing 25 (4), 259-268, 2009
1312009
An analytical approach to the partial scan problem
A Kunzmann, HJ Wunderlich
Journal of Electronic Testing 1 (2), 163-174, 1990
1301990
Self test using unequiprobable random patterns
HJ Wunderlich
1271987
X-masking during logic BIST and its impact on defect coverage
Y Tang, HJ Wunderlich, H Vranken, F Hapke, M Wittke, P Engelke, ...
2004 International Conferce on Test, 442-451, 2004
1212004
An integrated built-in test and repair approach for memories with 2D redundancy
P Ohler, S Hellebrand, HJ Wunderlich
12th IEEE European Test Symposium (ETS'07), 91-96, 2007
1132007
Application of deterministic logic BIST on industrial circuits
G Kiefer, H Vranken, EJ Marinissen, HJ Wunderlich
Journal of Electronic Testing 17 (3), 351-362, 2001
1112001
Design and architectures for dependable embedded systems
J Henkel, L Bauer, J Becker, O Bringmann, U Brinkschulte, S Chakraborty, ...
Proceedings of the seventh IEEE/ACM/IFIP international conference on …, 2011
1052011
Tailoring ATPG for embedded testing
R Dorsch, HJ Wunderlich
Proceedings International Test Conference 2001 (Cat. No. 01CH37260), 530-537, 2001
1022001
Mixed-mode BIST using embedded processors
S Hellebrand, HJ Wunderlich, A Hertwig
On-Line Testing for VLSI, 127-138, 1998
1011998
Accumulator based deterministic BIST
R Dorsch, HJ Wunderlich
Proceedings International Test Conference 1998 (IEEE Cat. No. 98CH36270 …, 1998
1001998
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Artiklar 1–20