Mehdi Alipour
Mehdi Alipour
Verified email at it.uu.se
TitleCited byYear
Non-speculative load-load reordering in TSO
A Ros, TE Carlson, M Alipour, S Kaxiras
ACM SIGARCH Computer Architecture News 45 (2), 187-200, 2017
172017
Design Space Exploration to Find the Optimum Cache and Register File Size for Embedded Applications
M Alipour, ME Salehi
9th Int'l Conf. Embedded Systems and Applications, ESA'11, las vegas, USA …, 2012
152012
Cache power and performance tradeoffs for embedded applications
M Alipour, ME Salehi, K Moshari
2011 IEEE International Conference on Computer Applications and Industrial …, 2011
102011
Performance per power optimum cache architecture for embedded applications, a design space exploration
M Alipour, K Moshari, MR Bagheri
2011 IEEE 2nd International Conference on Networked Embedded Systems for …, 2011
72011
Exploring the performance limits of out-of-order commit
M Alipour, TE Carlson, S Kaxiras
Proceedings of the Computing Frontiers Conference, 211-220, 2017
62017
Multi objective design space exploration of cache for embedded applications
M Alipour, H Taghdisi, SH Sadeghzadeh
2012 25th IEEE Canadian Conference on Electrical and Computer Engineering …, 2012
52012
Arvind,“
S Zhang, M Vijayaraghavan, A Wright, M Alipour
Weak memory models: Balancing definitional simplicity and implementation …, 2017
42017
Effect of Thread Level Parallelism on the Performance of Optimum Architecture for Embedded Applications
M Alipour, H Taghdisi
International Journal of Embedded Systems and Applications (IJESA) Vol.2 …, 2012
42012
Ghost loads: what is the cost of invisible speculation?
C Sakalis, M Alipour, A Ros, A Jimborean, S Kaxiras, M Själander
Proceedings of the 16th ACM International Conference on Computing Frontiers …, 2019
22019
Constructing a weak memory model
S Zhang, M Vijayaraghavan, A Wright, M Alipour
2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture …, 2018
22018
Maximizing Limited Resources: a Limit-Based Study and Taxonomy of Out-of-Order Commit
M Alipour, TE Carlson, D Black-Schaffer, S Kaxiras
Journal of Signal Processing Systems 91 (3-4), 379-397, 2019
12019
Freeway: Maximizing MLP for Slice-Out-of-Order Execution
R Kumar, M Alipour, D Black-Schaffer
2019 IEEE International Symposium on High Performance Computer Architecture …, 2019
12019
Delay and Bypass: Ready and Criticality Aware Instruction Scheduling in Out-of-Order Processors
M Alipour, R Kumar, S Kaxiras, D Black-Schaffer
The 26th IEEE International Symposium on High-Performance Computer …, 2020
2020
FIFOrder MicroArchitecture: Ready-Aware Instruction Scheduling for OoO Processors
M Alipour, R Kumar, S Kaxiras, D Black-Schaffer
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 716-721, 2019
2019
Non-speculative load reordering in total store ordering
S Kaxiras, TE Carlson, M Alipour, A Ros
IEEE Micro 38 (3), 48-57, 2018
2018
A taxonomy of out-of-order instruction commit
M Alipour, TE Carlson, S Kaxiras
2017 IEEE International Symposium on Performance Analysis of Systems and …, 2017
2017
Evaluating thread level parallelism based on optimum cache architecture
M Alipour, BA Khorramshahi, F Karimi, Z Mirzaei, A Vaghari
2012 International Symposium on Computer Applications and Industrial …, 2012
2012
Performance-optimum superscalar architecture for embedded applications
M Alipour, ME Salehi
International Journal of Applied Research on Technology and computing …, 2012
2012
Congestion and track usage improvement of large FPGAs using metro-on-FPGA methodology
M Alipour, M Haji Seyed Javadi, A Jahanian
Proceedings of the 21st edition of the great lakes symposium on Great lakes …, 2011
2011
A Power-Aware Cache and Register File Design Space Exploration
M Alipour, ME Salehi
JOURNAL OF COMPUTER AND ROBOTICS 4 (1), 39-46, 2011
2011
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Articles 1–20