| Retiming and clock scheduling to minimize simultaneous switching A Mukherjee, R Sankaranarayan IEEE International SOC Conference, 2004. Proceedings., 259-262, 2004 | 15 | 2004 |
| A single-VDD ultra-low energy sub-threshold FPGA R Sankaranarayanan, MR Guthaus 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip …, 2012 | 5 | 2012 |
| Energy Savings and Performance Improvement in Subthreshold Using Adaptive Body Bias R Sankaranarayanan, MR Guthaus Proceedings of the on Great Lakes Symposium on VLSI 2017, 431-434, 2017 | 1 | 2017 |
| Layout-aware gate-sizing and buffer insertion for low-power low-noise DSM circuits A Mukhejee, R Sankaranarayan, KR Dusety IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings., 273-274, 2003 | 1 | 2003 |
| Reducing Variability in Subthreshold Circuits R Sankaranarayanan UC Santa Cruz, 2017 | | 2017 |
| Retiming and Clock-scheduling to Minimize Simultaneous Switching Noise in Deep Sub-micron Circuits R Sankaranarayanan University of North Carolina at Charlotte, 2004 | | 2004 |
| A practical CAD technique for reducing power/ground noise in DSM circuits A Mukherjee, KR Dusety, R Sankaranarayan Proceedings of the 13th ACM Great Lakes symposium on VLSI, 96-99, 2003 | | 2003 |
| Matthew Guthaus, UC Santa Cruz, USA SMS Kang, R Sankaranarayanan, K Pedrotti | | |
