Brian Zimmer
Brian Zimmer
Research Scientist, NVIDIA
Verifierad e-postadress på eecs.berkeley.edu
TitelCiteras avÅr
SRAM assist techniques for operation in a wide voltage range in 28-nm CMOS
B Zimmer, SO Toh, H Vo, Y Lee, O Thomas, K Asanovic, B Nikolic
IEEE Transactions on Circuits and Systems II: Express Briefs 59 (12), 853-857, 2012
642012
System and method for performing SRAM write assist
BM Zimmer, ME Sinangil
US Patent 8,861,290, 2014
572014
An agile approach to building RISC-V microprocessors
Y Lee, A Waterman, H Cook, B Zimmer, B Keller, A Puggelli, J Kwak, ...
IEEE Micro 36 (2), 8-20, 2016
382016
A RISC-V vector processor with simultaneous-switching switched-capacitor DC–DC converters in 28 nm FDSOI
B Zimmer, Y Lee, A Puggelli, J Kwak, R Jevtić, B Keller, S Bailey, ...
IEEE Journal of Solid-State Circuits 51 (4), 930-942, 2016
372016
A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI
B Zimmer, Y Lee, A Puggelli, J Kwak, R Jevtic, B Keller, S Bailey, ...
2015 Symposium on VLSI Circuits (VLSI Circuits), C316-C317, 2015
322015
6T SRAM design for wide voltage range in 28nm FDSOI
O Thomas, B Zimmer, B Pelloux-Prayer, N Planes, KC Akyel, L Ciampolini, ...
2012 IEEE International SOI Conference (SOI), 1-2, 2012
252012
Strober: fast and accurate sample-based energy simulation for arbitrary RTL
D Kim, A Izraelevitz, C Celio, H Kim, B Zimmer, Y Lee, J Bachrach, ...
2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture …, 2016
242016
A 28 nm 2 Mbit 6 T SRAM with highly configurable low-voltage write-ability assist implementation and capacitor-based sense-amplifier input offset compensation
ME Sinangil, JW Poulton, MR Fojtik, TH Greer III, SG Tell, AJ Gotterba, ...
IEEE Journal of Solid-State Circuits 51 (2), 557-567, 2015
152015
Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking
Y Lee, B Zimmer, A Waterman, A Puggelli, J Kwak, R Jevtic, B Keller, ...
2015 IEEE Hot Chips 27 Symposium (HCS), 1-45, 2015
122015
Drugs for treating viral infections
VS Georgiev
US Patent 6,596,771, 2003
122003
A RISC-V processor SoC with integrated power management at submicrosecond timescales in 28 nm FD-SOI
B Keller, M Cochet, B Zimmer, J Kwak, A Puggelli, Y Lee, M Blagojević, ...
IEEE Journal of Solid-State Circuits 52 (7), 1863-1875, 2017
112017
A 1.17 pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off-and on-package communication in 16nm CMOS using a process-and temperature-adaptive voltage regulator
JM Wilson, WJ Turner, JW Poulton, B Zimmer, X Chen, SS Kudva, S Song, ...
2018 IEEE International Solid-State Circuits Conference-(ISSCC), 276-278, 2018
102018
Dynamic single-p-well SRAM bitcell characterization with back-bias adjustment for optimized wide-voltage-range SRAM operation in 28nm UTBB FD-SOI
O Thomas, B Zimmer, SO Toh, L Ciampolini, N Planes, R Ranica, ...
2014 IEEE International Electron Devices Meeting, 3.4. 1-3.4. 4, 2014
92014
A double-tail sense amplifier for low-voltage SRAM in 28nm technology
PF Chiu, B Zimmer, B Nikolić
2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), 181-184, 2016
82016
A modular digital VLSI flow for high-productivity SoC design
B Khailany, E Krimer, R Venkatesan, J Clemons, JS Emer, M Fojtik, ...
2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), 1-6, 2018
72018
Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC
B Keller, M Cochet, B Zimmer, Y Lee, M Blagojevic, J Kwak, A Puggelli, ...
ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 269-272, 2016
62016
Joint impact of random variations and RTN on dynamic writeability in 28nm bulk and FDSOI SRAM
B Zimmer, O Thomas, SO Toh, T Vincent, K Asanović, B Nikolić
2014 44th European Solid State Device Research Conference (ESSDERC), 98-101, 2014
62014
Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects
WJ Turner, JW Poulton, JM Wilson, X Chen, SG Tell, M Fojtik, TH Greer, ...
2018 IEEE Custom Integrated Circuits Conference (CICC), 1-8, 2018
52018
Reprogrammable Redundancy for SRAM-Based Cache Reduction in a 28-nm RISC-V Processor
B Zimmer, PF Chiu, B Nikolić, K Asanović
IEEE Journal of Solid-State Circuits 52 (10), 2589-2600, 2017
52017
An analytical model for hardened latch selection and exploration
M Sullivan, B Zimmer, S Hari, T Tsai, SW Keckler
Proc. Workshop Silicon Errors Logic Syst. Effects (SELSE), 1-7, 2016
52016
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