| Performance/price estimates for cortex-scale hardware: a design space exploration MS Zaveri, D Hammerstrom Neural Networks 24 (3), 291-304, 2011 | 27 | 2011 |
| Cmol/cmos implementations of bayesian polytree inference: Digital and mixed-signal architectures and performance/price MS Zaveri, D Hammerstrom IEEE Transactions on Nanotechnology 9 (2), 194-211, 2009 | 25 | 2009 |
| CMOL/CMOS Implementations of Bayesian Polytree Inference: Digital & Mixed-Signal Architectures and Performance/Price MS Zaveri, D Hammerstrom | 25 | 2008 |
| FPGA implementation of high-performance, resource-efficient Radix-16 CORDIC rotator based FFT algorithm A Changela, M Zaveri, D Verma Integration 73, 89-100, 2020 | 21 | 2020 |
| CMOS/CMOL architectures for spiking cortical column C Gao, MS Zaveri, D Hammerstrom 2008 IEEE International Joint Conference on Neural Networks (IEEE World …, 2008 | 19 | 2008 |
| Improving the performance of transmission gate and hybrid CMOS Full Adders in chain and tree structure architectures M Mewada, M Zaveri, R Thakker Integration 69, 381-392, 2019 | 17 | 2019 |
| Verilog implementation of a node of hierarchical temporal memory P Vyas, M Zaveri Asian Journal of Computer Science & Information Technology 3 (7), 2013 | 13 | 2013 |
| FPGA implementation of asynchronous mousetrap pipelined radix-2 CORDIC algorithm A Changela, M Zaveri, A Lakhlani 2018 International Conference on Current Trends towards Converging …, 2018 | 12 | 2018 |
| Mixed-radix, virtually scaling-free CORDIC algorithm based rotator for DSP applications A Changela, M Zaveri, D Verma Integration 78, 70-83, 2021 | 11 | 2021 |
| An input test pattern for characterization of a full-adder and n-bit ripple carry adder M Mewada, M Zaveri 2016 International Conference on Advances in Computing, Communications and …, 2016 | 10 | 2016 |
| A low-power high-speed hybrid full adder M Mewada, M Zaveri 2016 20th International Symposium on VLSI Design and Test (VDAT), 1-2, 2016 | 8 | 2016 |
| ASIC implementation of high performance radix-8 CORDIC algorithm A Changela, M Zaveri, A Lakhlani 2018 International Conference on Advances in Computing, Communications and …, 2018 | 7 | 2018 |
| Prospects for building cortex-scale CMOL/CMOS circuits: a design space exploration D Hammerstrom, MS Zaveri 2009 NORCHIP, 1-8, 2009 | 7 | 2009 |
| A comparative study on CORDIC algorithms and applications A Changela, M Zaveri, D Verma Journal of Circuits, Systems and Computers 32 (05), 2330002, 2023 | 6 | 2023 |
| Transmission gate and hybrid cmos full adder characterization and power-delay product estimation based on mathematical model M Mewada, M Zaveri, R Gandhi, R Thakker Procedia Computer Science 171, 999-1008, 2020 | 6 | 2020 |
| Analysis of increased parallelism in fpga implementation of neural networks for environment/noise classification and removal NB Ambasana, M Zaveri 2012 Nirma University International Conference on Engineering (NUiCONE), 1-5, 2012 | 4 | 2012 |
| Bayesian Memory, a Possible Hardware Building Block for Intelligent Systems. D Hammerstrom, M Zaveri AAAI Fall Symposium: Biologically Inspired Cognitive Architectures, 81, 2008 | 4 | 2008 |
| Experiments with multinational cross-course project MS Raval, T Kaya, M Zaveri, P Sharma 2020 IEEE International Conference on Teaching, Assessment, and Learning for …, 2020 | 3 | 2020 |
| An improved input test pattern for characterization of full adder circuits M Mewada, M Zaveri International Journal of Research and Scientific Innovation-IJRSI 3 (1), 222-226, 2015 | 3 | 2015 |
| CMOL/CMOS hardware architectures and performance/price for Bayesian memory-The building block of intelligent systems MS Zaveri Portland State University, 2009 | 3 | 2009 |
Dan HammerstromProfessor Emeritus, Portland State UniversityVerified email at pdx.edu
