| A 14-transistor CMOS full adder with full voltage-swing nodes M Vesterbacka 1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and …, 1999 | 198 | 1999 |
| A multiplexer based decoder for flash analog-to-digital converters E Sail, M Vesterbacka 2004 IEEE Region 10 Conference TENCON 2004. 500, 250-253, 2004 | 133 | 2004 |
| Thermometer-to-binary decoders for flash analog-to-digital converters E Sall, M Vesterbacka 2007 18th European Conference on Circuit Theory and Design, 240-243, 2007 | 81 | 2007 |
| A study of digital decoders in flash analog-to-digital converters E Sall, M Vesterbacka, KO Andersson 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No …, 2004 | 78 | 2004 |
| Time-mode analog-to-digital conversion using standard cells V Unnikrishnan, M Vesterbacka IEEE Transactions on Circuits and Systems I: Regular Papers 61 (12), 3348-3357, 2014 | 62 | 2014 |
| A Vernier time-to-digital converter with delay latch chain architecture NU Andersson, M Vesterbacka IEEE Transactions on Circuits and Systems II: Express Briefs 61 (10), 773-777, 2014 | 58 | 2014 |
| Modeling of glitches due to rise/fall asymmetry in current-steering digital-to-analog converters KO Andersson, M Vesterbacka IEEE Transactions on Circuits and Systems I: Regular Papers 52 (11), 2265-2275, 2005 | 40 | 2005 |
| Om implementation of maximally fast wave digital filters M Vesterbacka Linköping University, 1997 | 37 | 1997 |
| Comparison of two thermometer-to-binary decoders for high-performance flash ADCs E Sall, M Vesterbacka 2005 NORCHIP, 253-256, 2005 | 27 | 2005 |
| Mitigation of sampling errors in VCO-based ADCs V Unnikrishnan, M Vesterbacka IEEE Transactions on Circuits and Systems I: Regular Papers 64 (7), 1730-1739, 2017 | 24 | 2017 |
| A new six-transistor CMOS XOR circuit with complementary output M Vesterbacka 42nd Midwest Symposium on Circuits and Systems (Cat. No. 99CH36356) 2, 796-799, 1999 | 24 | 1999 |
| Dynamic element matching in D/A converters with restricted scrambling M Vesterbacka, M Rudberg, JJ Wikner, NU Andersson ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and …, 2000 | 23 | 2000 |
| Implementation of fast bit-serial lattice wave digital filters M Vesterbacka, K Palmkvist, P Sandberg, L Wanhammar 1994 IEEE International Symposium on Circuits and Systems (ISCAS) 2, 113-116, 1994 | 23 | 1994 |
| Maximally fast, bit-serial lattice wave digital filters M Vesterbacka, K Palmkvist, L Wanhammar 1996 IEEE Digital Signal Processing Workshop Proceedings, 207-210, 1996 | 18 | 1996 |
| Implementation of a bit-serial FFT processor with a hierarchical control structure J Melander, T Widhe, P Sandberg, K Palmkvist, M Vesterbacka, ... Proc. European Conf. on Circuit Theory and Design, ECCTD ‘95, Istanbul …, 1995 | 18 | 1995 |
| A robust differential scan flip-flop M Vesterbacka 1999 IEEE International Symposium on Circuits and Systems (ISCAS) 1, 334-337, 1999 | 17 | 1999 |
| Realization of serial/parallel multipliers with fixed coefficients M Vesterbacka, K Palmkvist, L Wanhammar Univ., 1993 | 17 | 1993 |
| Implementation of bit-serial adders using robust differential logic M Karlsson, M Vesterbacka, L Wanhammar Proc. IEEE Nordic Event in ASIC Design Conf., NORCHIP 97, 10-11, 1997 | 16 | 1997 |
| A strategy for reducing clock noise in mixed-signal circuits E Backenius, M Vesterbacka, R Hagglund The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002 …, 2002 | 15 | 2002 |
| Models and implementation of a dynamic element matching DAC NU Andersson, KO Andersson, M Vesterbacka, JJ Wikner Analog Integrated Circuits and Signal Processing 34, 7-16, 2003 | 14 | 2003 |
