| 22.3 A 20GHz-BW 6b 10GS/s 32mW time-interleaved SAR ADC with Master T&H in 28nm UTBB FDSOI technology S Le Tual, PN Singh, C Curis, P Dautriche Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 …, 2014 | 92 | 2014 |
| 20mW, 125 Msps, 10 bit Pipelined ADC in 65nm Standard Digital CMOS Process PN Singh, A Kumar, C Debnath, R Malik Custom Integrated Circuits Conference, 2007. CICC'07. IEEE, 189-192, 2007 | 32 | 2007 |
| A 0.065-mm²²² 19.8-mW Single-Channel Calibration-Free 12-b 600-MS/s ADC in 28-nm UTBB FD-SOI Using FBB A Kumar, C Debnath, PN Singh, V Bhatia, S Chaudhary, V Jain, S Le Tual, ... IEEE Journal of Solid-State Circuits, 2017 | 18 | 2017 |
| A 0.065mm2 19.8mW single channel calibration-free 12b 600MS/s ADC in 28nm UTBB FDSOI using FBB A Kumar, C Debnath, PN Singh, V Bhatia, S Chaudhary, V Jain, S Le Tual, ... European Solid-State Circuits Conference, ESSCIRC Conference 2016: 42nd, 165-168, 2016 | 18 | 2016 |
| A 3GS/s, 9b, 1.2 V single supply, pure binary DAC with> 50dB SFDR up to 1.5 GHz in 65nm CMOS S Le Tual, PN Singh, A Bal, C Garnier VLSI Circuits (VLSIC), 2011 Symposium on, 64-65, 2011 | 18 | 2011 |
| Adaptive delay based asynchronous successive approximation analog-to-digital converter PN Singh, AS Kumar, C Debnath, R Malik US Patent 9,258,008, 2016 | 17 | 2016 |
| An analysis of power supply induced jitter for a voltage mode driver in high speed serial links JN Tripathi, VK Sharma, H Advani, PN Singh, H Shrimali, R Malik Signal and Power Integrity (SPI), 2016 IEEE 20th Workshop on, 1-4, 2016 | 15 | 2016 |
| A 12b 1.7 GS/s two-times interleaved DAC with<-62dBc IM3 across Nyquist using a single 1.2 V supply E Olieman, AJ Annema, B Nauta, A Bal, PN Singh Solid-State Circuits Conference (A-SSCC), 2013 IEEE Asian, 81-84, 2013 | 12 | 2013 |
| A 12b 1.7 GS/s two-times interleaved DAC with E Olieman, AJ Annema, B Nauta, A Bal, PN Singh 2013 IEEE Asian Solid-State Circuits Conference, 2013 | 12 | 2013 |
| A 1.2 v 11b 100Msps 15mW ADC realized using 2.5 b pipelined stage followed by time interleaved SAR in 65nm digital CMOS process PN Singh, A Kumar, C Debnath, R Malik Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE, 305-308, 2008 | 11 | 2008 |
| Differential successive approximation analog to digital converter S Le Tual, PN Singh, O Zabroda, N Vannucci US Patent 8,497,795, 2013 | 10 | 2013 |
| Self-calibrated digital-to-analog converter PN Singh, SSB Kaleru, A Bal, M Singh, R Malik US Patent 9,379,728, 2016 | 8 | 2016 |
| Calibration method and circuit C Debnath, PN Singh US Patent 8,576,102, 2013 | 8 | 2013 |
| Compact sar adc S Le Tual, M Boulemnakher, PN Singh US Patent 8,514,123, 2013 | 7 | 2013 |
| Variable delay element S Le Tual, PN Singh US Patent 9,432,008, 2016 | 5 | 2016 |
| Analog to digital converter PN Singh, R Jain, AK Sharma, C Dash US Patent App. 17/105,359, 2021 | 4 | 2021 |
| Current steering digital to analog converter with decoder free quad switching PN Singh, V Tripathi, A Kumar, R Malik US Patent 10,148,277, 2018 | 4 | 2018 |
| Circuit and method for generating reference signals for hybrid analog-to-digital convertors A Kumar, C Debnath, PN Singh US Patent 9,705,520, 2017 | 4 | 2017 |
| Scheme for improving settling behavior of gain boosted fully differential operational amplifier PN Singh, C Debnath, R Malik, AJ D'souza US Patent 7,737,780, 2010 | 4 | 2010 |
| Current steering digital to analog converter (dac) system to perform dac static linearity calibration PN Singh, A Ahmad, C Dash US Patent App. 17/105,363, 2021 | 3 | 2021 |
Rakesh MALIKSTMicroelectronicsVerified email at st.com
