Daniel Grosse
Daniel Grosse
Senior Reasearcher, University of Bremen, Germany
Verifierad e-postadress på informatik.uni-bremen.de - Startsida
TitelCiteras avÅr
RevLib: An online resource for reversible functions and reversible circuits
R Wille, D Große, L Teuber, GW Dueck, R Drechsler
38th International Symposium on Multiple Valued Logic (ismvl 2008), 220-225, 2008
3022008
Exact multiple-control toffoli network synthesis with SAT techniques
D Große, R Wille, GW Dueck, R Drechsler
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2009
1762009
Proving transaction and system-level properties of untimed SystemC TLM designs
D Große, HM Le, R Drechsler
Eighth ACM/IEEE International Conference on Formal Methods and Models for …, 2010
802010
Equivalence checking of reversible circuits
R Wille, D Große, DM Miller, R Drechsler
2009 39th International Symposium on Multiple-Valued Logic, 324-330, 2009
792009
Formal verification of LTL formulas for SystemC designs
D Große, R Drechsler
Proceedings of the 2003 International Symposium on Circuits and Systems …, 2003
572003
Fast exact Toffoli network synthesis of reversible logic
R Wille, D Grobe
2007 IEEE/ACM International Conference on Computer-Aided Design, 60-64, 2007
562007
Quantified synthesis of reversible logic
R Wille, HM Le, GW Dueck, D GroBe
2008 Design, Automation and Test in Europe, 1015-1020, 2008
552008
HW/SW co-verification of embedded systems using bounded model checking
D Groβe, U Kühne, R Drechsler
Proceedings of the 16th ACM Great Lakes symposium on VLSI, 43-48, 2006
552006
Exact SAT-based Toffoli network synthesis
D Große, X Chen, GW Dueck, R Drechsler
Proceedings of the 17th ACM Great Lakes symposium on VLSI, 96-101, 2007
502007
Reachability analysis for formal verification of SystemC
R Drechsler, D Große
Proceedings Euromicro Symposium on Digital System Design. Architectures …, 2002
502002
Formal verification of integer multipliers by combining Gröbner basis with logic reduction
A Sayed-Ahmed, D Große, U Kühne, M Soeken, R Drechsler
Proceedings of the 2016 Conference on Design, Automation & Test in Europe …, 2016
482016
Reversible logic synthesis with output permutation
R Wille, D Große, GW Dueck, R Drechsler
2009 22nd International Conference on VLSI Design, 189-194, 2009
462009
SWORD: A SAT like prover using word level information
R Wille, G Fey, D Große, S Eggersglüß, R Drechsler
VLSI-SoC: Advanced Topics on Systems on a Chip, 1-17, 2009
452009
ParSyC: an efficient SystemC parser
G Fey, D Große, T Cassens, C Genz, T Warode, R Drechsler
In Workshop on Synthesis And System Integration of Mixed Information …, 2004
452004
Exact synthesis of elementary quantum gate circuits for reversible functions with don't cares
D Große, R Wille, GW Dueck, R Drechsler
38th International Symposium on Multiple Valued Logic (ismvl 2008), 214-219, 2008
432008
CheckSyC: An efficient property checker for RTL SystemC designs
D Große, R Drechsler
2005 IEEE International Symposium on Circuits and Systems, 4167-4170, 2005
432005
WoLFram-a word level framework for formal verification
A Sülflow, U Kühne, G Fey, D Grosse, R Drechsler
2009 IEEE/IFIP International Symposium on Rapid System Prototyping, 11-17, 2009
422009
Verifying SystemC using an intermediate verification language and symbolic simulation
HM Le, D Große, V Herdt, R Drechsler
2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2013
402013
Efficient Automatic Visualization of SystemC Designs.
D Große, R Drechsler, L Linhard, G Angst
FDL, 646-658, 2003
402003
Quality-Driven SystemC Design
D Große, R Drechsler
Springer, 2010
372010
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Artiklar 1–20