Fan Chen
Fan Chen
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Direct Observation of 2D Electrostatics and Ohmic Contacts in Template-Grown Graphene/WS2 Heterostructures
C Zheng, Q Zhang, B Weber, H Ilatikhameneh, F Chen, H Sahasrabudhe, ...
ACS nano 11 (3), 2785-2793, 2017
Thickness Engineered Tunnel Field-Effect Transistors based on Phosphorene
F Chen, H Ilatikhameneh, TA Ameen, G Klimeck, R Rahman
IEEE Electron Device Letters 2016, 2016
Configurable Electrostatically Doped High Performance Bilayer Graphene Tunnel FET
F Chen, H Ilatikhameneh, G Klimeck, Z Chen, R Rahman
IEEE Journal of the Electron Devices Society 4 (3), 125-128, 2016
First principles study and empirical parametrization of twisted bilayer MoS2 based on band-unfolding
Y Tan, F Chen, A Ghosh
Applied Physics Letters 109 (10), 101601, 2016
Switching Mechanism and the Scalability of vertical-TFETs
F Chen, H Ilatikhameneh, Y Tan, G Klimeck, R Rahman
IEEE Transaction on Electron Devices, 2018
Dramatic impact of dimensionality on the electrostatics of PN junctions and its sensing and switching applications
H Ilatikhameneh, T Ameen, F Chen, H Sahasrabudhe, G Klimeck, ...
IEEE Transactions on Nanotechnology 17 (2), 293-298, 2018
Transport in vertically stacked hetero-structures from 2D materials
F Chen, H Ilatikhameneh, Y Tan, D Valencia, G Klimeck, R Rahman
33rd International Conference on the Physics of Semiconductors (ICPS), 2016
In-surface confinement of topological insulator nanowire surface states
F Chen, L Jauregui, Y Tan, M Manfra, Y Chen, K Gerhard, T Kubis
Applied Physics Letters 107 (12), 121605, 2015
STT-MRAM design technology co-optimization for hardware neural networks
N Xu, Y Lu, W Qi, Z Jiang, X Peng, F Chen, J Wang, W Choi, S Yu, DS Kim
2018 IEEE International Electron Devices Meeting (IEDM), 15.3. 1-15.3. 4, 2018
Achieving a higher performance in bilayer graphene FET -- strain engineering
F Chen, H Ilatikhameneh, G Klimeck, R Rahman, T Chu, Z Chen
International Conference on Simulation of Semiconductor Processes and …, 2015
Electrically Doped 2D Material Tunnel Transistors
H Ilatikhameneh, F Chen, J Appenzeller, R Rahman, G Klimeck
International Workshop on Computational Electronics (IWCE), 2015
NEMO5: Why must we treat topological insulator nanowires atomically?
F Chen, M Manfra, G Klimeck, T Kubis
International Workshop on Computational Electronics (IWCE), 2015
Transport Properties of Bilayer Graphene Field Effect Transistor
FW Chen, H Ilatikhameneh, T Chu, R Rahman, J Appenzeller, Z Chen, ...
Novel III-N heterostructure devices for low-power logic and more
P Fay, W Li, L Cao, K Pourang, SM Islam, C Lund, S Saima, ...
2016 IEEE 16th International Conference on Nanotechnology (IEEE-NANO), 767-769, 2016
Assessing Intrinsic and Extrinsic End-of-Life Risk Using Functional SRAM Wafer Level Testing
YM Randriamihaja, W McMahon, S Balasubramanian, T Nigam, ...
IEEE International Reliability Physics Symposium, 6A. 5.1-6A. 5.4, 2015
Rare-failure oriented STT-MRAM technology optimization
N Xu, F Chen, D Apalkov, W Qi, J Wang, Z Jiang, W Choi, DS Kim
2018 IEEE Symposium on VLSI Technology, 187-188, 2018
Dramatic Impact of Dimensionality on the Electrostatics of PN Junctions
H Ilatikhameneh, T Ameen, F Chen, H Sahasrabudhe, G Klimeck, ...
arXiv preprint arXiv:1704.05488, 2017
1d heterostructure tool
AG Akkala, S Steiger, JMD Sellier, S Lee, M Povolotskyi, TC Kubis, H Park, ...
Systems and methods for wafer map analysis
XU Nuo, C Fan, W Qi, J Kim, J Wang, Y Lu, C Woosung
US Patent App. 16/107,942, 2019
Hole Mobility Model for Si Double-Gate Junctionless Transistors
F Chen, K Wei, WEI Sha, JZ Huang
IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS …, 2017
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Artiklar 1–20