Mathias Soeken
Mathias Soeken
Microsoft, EPFL
Verifierad e-postadress på epfl.ch - Startsida
TitelCiteras avÅr
Verifying UML/OCL models using Boolean satisfiability
M Soeken, R Wille, M Kuhlmann, M Gogolla, R Drechsler
Proceedings of the Conference on Design, Automation and Test in Europe, 1341 …, 2010
1492010
Synthesis of reversible circuits with minimal lines for large functions
M Soeken, R Wille, C Hilken, N Przigoda, R Drechsler
Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific, 85-92, 2012
992012
RevKit: A Toolkit for Reversible Circuit Design.
M Soeken, S Frehse, R Wille, R Drechsler
Multiple-Valued Logic and Soft Computing 18 (1), 55-65, 2012
982012
Assisted behavior driven development using natural language processing
M Soeken, R Wille, R Drechsler
International Conference on Modelling Techniques and Tools for Computer …, 2012
762012
Verifying dynamic aspects of UML models.
M Soeken, R Wille, R Drechsler
DATE, 1077-1082, 2011
672011
RevKit: an open source toolkit for the design of reversible circuits
M Soeken, S Frehse, R Wille, R Drechsler
International Workshop on Reversible Computation, 64-76, 2011
652011
Reducing the number of lines in reversible circuits
R Wille, M Soeken, R Drechsler
Design Automation Conference (DAC), 2010 47th ACM/IEEE, 647-652, 2010
612010
Encoding OCL data types for SAT-based verification of UML/OCL models
M Soeken, R Wille, R Drechsler
International Conference on Tests and Proofs, 152-170, 2011
562011
Formal Verification of Integer Multipliers by Combining Grobner Basis with Logic Reduction
A Sayed-Ahmed, D Große, U Kühne, M Soeken, R Drechsler
54*
Formal Specification Level: Towards verification-driven design based on natural language processing
R Drechsler, M Soeken, R Wille
Specification and Design Languages (FDL), 2012 Forum on, 53-58, 2012
482012
Fast logic synthesis for RRAM-based in-memory computing using Majority-Inverter Graphs
S Shirinzadeh, M Soeken, PE Gaillardon, R Drechsler
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 948-953, 2016
452016
Trading off circuit lines and gate costs in the synthesis of reversible logic
R Wille, M Soeken, DM Miller, R Drechsler
Integration, the VLSI Journal 47 (2), 284-294, 2014
452014
Specification-driven model transformation testing
E Guerra, M Soeken
Software & Systems Modeling 14 (2), 623-644, 2015
422015
Hierarchical synthesis of reversible circuits using positive and negative Davio decomposition
M Soeken, R Wille, R Drechsler
Design and Test Workshop (IDT), 2010 5th International, 143-148, 2010
422010
Embedding of large Boolean functions for reversible logic
M Soeken, R Wille, O Keszocze, DM Miller, R Drechsler
ACM Journal on Emerging Technologies in Computing Systems (JETC) 12 (4), 41, 2016
402016
BDD Minimization for Approximate Computing
M Soeken, D Große, A Chandrasekharan, R Drechsler
38*
Ancilla-free synthesis of large reversible functions using binary decision diagrams
M Soeken, L Tague, GW Dueck, R Drechsler
Journal of Symbolic Computation 73, 1-26, 2016
372016
Improving the mapping of reversible circuits to quantum circuits using multiple target lines
R Wille, M Soeken, C Otterstedt, R Drechsler
Design Automation Conference (ASP-DAC), 2013 18th Asia and South Pacific …, 2013
352013
Exact synthesis of majority-inverter graphs and its applications
M Soeken, L Amaru, PE Gaillardon, G De Micheli
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017
342017
Approximation-aware Rewriting of AIGs for Error Tolerant Applications
A Chandrasekharan, M Soeken, D Große, R Drechsler
34*
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Artiklar 1–20