| Design and comparison of three 20-Gb/s backplane transceivers for duobinary, PAM4, and NRZ data J Lee, MS Chen, HD Wang IEEE Journal of Solid-State Circuits 43 (9), 2120-2133, 2008 | 164 | 2008 |
| A fully-integrated 40-Gb/s transceiver in 65-nm CMOS technology MS Chen, YN Shih, CL Lin, HW Hung, J Lee IEEE Journal of solid-state circuits 47 (3), 627-640, 2011 | 105 | 2011 |
| A 0.1-1.5 GHz 8-bit inverter-based digital-to-phase converter using harmonic rejection AAH Ming-Shuan Chen, CKK Yang 2012 IEEE Asian Solid State Circuits Conference (A-SSCC), 2012 | 60* | 2012 |
| A 50–64 Gb/s serializing transmitter with a 4-tap, LC-ladder-filter-based FFE in 65 nm CMOS technology MS Chen, CKK Yang IEEE Journal of Solid-State Circuits 50 (8), 1903-1916, 2015 | 53 | 2015 |
| A 32–48 Gb/s serializing transmitter using multiphase serialization in 65 nm CMOS technology AA Hafez, MS Chen, CKK Yang IEEE Journal of Solid-State Circuits 50 (3), 763-775, 2015 | 45 | 2015 |
| A 32-to-48Gb/s serializing transmitter using multiphase sampling in 65nm CMOS AA Hafez, MS Chen, CKK Yang 2013 IEEE International Solid-State Circuits Conference Digest of Technical …, 2013 | 40 | 2013 |
| A 40Gb/s TX and RX chip set in 65nm CMOS MS Chen, YN Shih, CL Lin, HW Hung, J Lee 2011 IEEE International Solid-State Circuits Conference, 146-148, 2011 | 26 | 2011 |
| A 20Gb/s duobinary transceiver in 90nm CMOS J Lee, MS Chen, HD Wang 2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008 | 21 | 2008 |
| A low-power highly multiplexed parallel PRBS generator MS Chen, CKK Yang Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 1-4, 2012 | 16 | 2012 |
| A low-PDP and low-area repeater using passive CTLE for on-chip interconnects MS Chen, MCF Chang, CKK Yang 2015 Symposium on VLSI Circuits (VLSI Circuits), C244-C245, 2015 | 13 | 2015 |
| A multi-phase multi-frequency clock generator using superharmonic injection locked multipath ring oscillators as frequency dividers AA Hafez, MS Chen, CKK Yang 2012 IEEE Asian Solid State Circuits Conference (A-SSCC), 289-292, 2012 | 10 | 2012 |
| A 50–64 Gb/s serializing transmitter with a 4-tap, LC-ladder-filter-based FFE in 65-nm CMOS MS Chen, CKK Yang Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 1-4, 2014 | 9 | 2014 |
| An architecture-reconfigurable 3b-to-7b 4GS/s-to-1.5 GS/s ADC using subtractor interleaving R Yousry, MS Chen, MCF Chang, CKK Yang 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC), 285-288, 2013 | 6 | 2013 |
| Phase interpolator MS Chen US Patent 9,208,130, 2015 | 4 | 2015 |
| Duobinary transceiver J Lee, MS Chen, HD Wang US Patent 8,416,840, 2013 | 3 | 2013 |
| Design of 60 Plus Gb/s Serial-Link Transmitters Using Filter Techniques MS Chen University of California, Los Angeles, 2015 | 1 | 2015 |
| ISSCC 2008/SESSION 5/HIGH-SPEED TRANSCEIVERS/5.3 J Lee, MS Chen, HD Wang | | |
Chih-Kong Ken YangProfessor of Electrical Engineering, UCLAVerified email at ee.ucla.edu
