Sudhir Satpathy
Sudhir Satpathy
Compute Silicon Architect, Facebook Reality Labs
Verifierad e-postadress på fb.com
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Catnap: Energy proportional multiple network-on-chip
R Das, S Narayanasamy, SK Satpathy, RG Dreslinski
ACM SIGARCH Computer Architecture News 41 (3), 320-331, 2013
1432013
16.2 A 0.19 pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS
SK Mathew, SK Satpathy, MA Anders, H Kaul, SK Hsu, A Agarwal, ...
2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014
1422014
Centip3De: A 3930DMIPS/W configurable near-threshold 3D stacked system with 64 ARM Cortex-M3 cores
D Fick, RG Dreslinski, B Giridhar, G Kim, S Seo, M Fojtik, S Satpathy, ...
2012 IEEE International Solid-State Circuits Conference, 190-192, 2012
1112012
2.4 Gbps, 7 mW all-digital PVT-variation tolerant true random number generator for 45 nm CMOS high-performance microprocessors
SK Mathew, S Srinivasan, MA Anders, H Kaul, SK Hsu, F Sheikh, ...
IEEE Journal of Solid-State Circuits 47 (11), 2807-2821, 2012
1072012
340 mv–1.1 v, 289 gbps/w, 2090-gate nanoaes hardware accelerator with area-optimized encrypt/decrypt gf (2 4) 2 polynomials in 22 nm tri-gate cmos
S Mathew, S Satpathy, V Suresh, M Anders, H Kaul, A Agarwal, S Hsu, ...
IEEE Journal of Solid-State Circuits 50 (4), 1048-1058, 2015
952015
A 340 mV-to-0.9 V 20.2 Tb/s source-synchronous hybrid packet/circuit-switched 16× 16 network-on-chip in 22 nm tri-gate CMOS
G Chen, MA Anders, H Kaul, SK Satpathy, SK Mathew, SK Hsu, ...
IEEE Journal of Solid-State Circuits 50 (1), 59-67, 2014
652014
Swizzle-switch networks for many-core systems
K Sewell, RG Dreslinski, T Manville, S Satpathy, N Pinckney, G Blake, ...
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 2 (2 …, 2012
652012
Centip3De: A cluster-based NTC architecture with 64 ARM Cortex-M3 cores in 3D stacked 130 nm CMOS
D Fick, RG Dreslinski, B Giridhar, G Kim, S Seo, M Fojtik, S Satpathy, ...
IEEE Journal of Solid-State Circuits 48 (1), 104-117, 2012
512012
Centip3de: A 64-core, 3d stacked near-threshold system
RG Dreslinski, D Fick, B Giridhar, G Kim, S Seo, M Fojtik, S Satpathy, ...
IEEE Micro 33 (2), 8-16, 2013
392013
Multiplexer, receiver, and multiplex transmission method
O Matsunaga
US Patent App. 10/129,018, 2003
352003
A 4.5 Tb/s 3.4 Tb/s/W 64× 64 switch fabric with self-updating least-recently-granted priority and quality-of-service arbitration in 45nm CMOS
S Satpathy, K Sewell, T Manville, YP Chen, R Dreslinski, D Sylvester, ...
2012 IEEE International Solid-State Circuits Conference, 478-480, 2012
332012
RNG: A 300–950 mV, 323 Gbps/W All-Digital Full-Entropy True Random Number Generator in 14 nm FinFET CMOS
SK Mathew, D Johnston, S Satpathy, V Suresh, P Newman, MA Anders, ...
IEEE Journal of Solid-State Circuits 51 (7), 1695-1704, 2016
312016
A 4-fJ/b delay-hardened physically unclonable function circuit with selective bit destabilization in 14-nm trigate CMOS
S Satpathy, SK Mathew, V Suresh, MA Anders, H Kaul, A Agarwal, ...
IEEE Journal of Solid-State Circuits 52 (4), 940-949, 2017
282017
Method, apparatus and system for a source-synchronous circuit-switched network on a chip (NOC)
GK Chen, MA Anders, H Kaul, SK Satpathy, RK Krishnamurthy
US Patent 9,652,425, 2017
242017
A 1.07 Tbit/s 128× 128 swizzle network for simd processors
S Satpathy, Z Foo, B Giridhar, R Dreslinski, D Sylvester, T Mudge, ...
2010 Symposium on VLSI Circuits, 81-82, 2010
242010
13fJ/bit probing-resilient 250K PUF array with soft darkbit masking for 1.94% bit-error in 22nm tri-gate CMOS
S Satpathy, S Mathew, J Li, P Koeberl, M Anders, H Kaul, G Chen, ...
ESSCIRC 2014-40th European Solid State Circuits Conference (ESSCIRC), 239-242, 2014
202014
Methods and apparatus to parallelize data decompression
V Gopal, JD Guilford, SK Satpathy, SK Mathew
US Patent 9,484,954, 2016
182016
Crossbar circuitry and method of operation of such crossbar circuitry
SK Satpathy, DT Blaauw, TN Mudge, DM Sylvester, RG Dreslinski
US Patent 8,108,585, 2012
162012
SWIFT: A 2.1 Tb/s 32× 32 self-arbitrating manycore interconnect fabric
S Satpathy, R Dreslinski, TC Ou, D Sylvester, T Mudge, D Blaauw
2011 Symposium on VLSI Circuits-Digest of Technical Papers, 138-139, 2011
142011
Priority-based routing
S Satpathy, H Kaul, M Anders, S Mathew, G Chen, R Krishnamurthy
US Patent 9,699,096, 2017
122017
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