| An SPIHT Algorithm with Huffman Encoder for Image compression and quality improvement using Retinex Algorithm TS A.Mallaiah, Sk.Shabbir 1st international Conference on AMELIORATIONS in communication and power …, 2012 | 24* | 2012 |
| Implementation of enhanced security algorithms in mobile ad hoc networks M Madhurya, BA Krishna, T Subhashini International Journal of Computer Network and Information Security 6 (2), 30-37, 2014 | 17 | 2014 |
| Implementation of data compression techniques in mobile ad hoc networks B Ruxanayasmin, BA Krishna, T Subhashini International Journal of Computer Applications 80 (8), 2013 | 14 | 2013 |
| A Novel Multimodal Medical Image Fusion Approach based on Phase Congruency and Directive Contrast in NSCT Domain MK S.Anitha ,T Subhashini International Journal of Computer Applications 129 (10), 30-35, 2015 | 8 | 2015 |
| Minimization of power consumption in mobile adhoc networks B Ruxanayasmin, B Krishna, T Subhashini International Journal of Computer Network and Information Security 6 (2), 38-44, 2014 | 6 | 2014 |
| Low-Power and rapid adders using new XOR and XNOR gates T Subhashini, M Kamaraju, K Babulu IEEE Trans. VLSI Des. Int. J. Eng. Res. Technol 12 (12), 2072-2076, 2019 | 4 | 2019 |
| Design and analysis of multiple port memory architecture for low power applications T Subhashini, M Kamaraju, K Babulu 2018 Conference on Signal Processing And Communication Engineering Systems …, 2018 | 1 | 2018 |
| Power optimized datapath units of hybrid embedded core architecture using clock gating technique T Subhashini, M Kamaraju Int. J. VLSI Des. Commun. Syst. 6 (6), 33-43, 2015 | 1 | 2015 |
| FPGA-Based 128-Bit RISC Processor Using Pipelining T Subhashini, M Kamaraju, K Babulu Advances in Signal Processing, Embedded Systems and IoT: Proceedings of …, 2023 | | 2023 |
| AREA AND POWER OPTIMIZED D-FLIP FLOP AND SUBTRACTOR T Subhashini, M Kamaraju, K Babulu INFORMATION TECHNOLOGY IN INDUSTRY 9 (1), 159-163, 2021 | | 2021 |
| Design of Power optimized Pipelined 64–bit Mini Instruction Set Programmable Processor (MISPP) T Subhashini, M Kamaraju, K Babulu Solid State Technology 64 (2), 762-774, 2021 | | 2021 |
| Power Optimized BCD adder Using Low Power Techniques KB T Subhashini, M Kamaraju Journal of Test Engineering and management, 8789 – 8795, 2020 | | 2020 |
| A New ALU Design using PNS-FCR: Static CMOS Logic for Microprocessors KB T Subhashini, M Kamaraju International Journal of Engineering and Advanced Technology (IJEAT) 8 (6S2 …, 2019 | | 2019 |
| Single Cycle Risc Micro Architecture Processor Using Clock Gating Technique KB T Subhashini, M Kamaraju International Journal of Scientific Technology Research 8 (12), 2326--2334, 2019 | | 2019 |
| A Novel Test Programs for Hybrid RISC Controller T Subhashini, M Kamaraju, K Babulu Microelectronics, Electromagnetics and Telecommunications: Proceedings of …, 2019 | | 2019 |
| Implementation of A Wallace Tree Approach for Data Aggregation in Wireless Sensor Nodes on ZED board and Send that Aggregated Data to the Sink through WSN Master Development … TS M Kamaraju, D Ramya Krishna International Journal for Research in Engineering Application & Management …, 2018 | | 2018 |
| A novel implementation of mixed ISA on FPGA T Subhashini, M Kamaraju, K Babulu 2017 International Conference on Communication and Signal Processing (ICCSP …, 2017 | | 2017 |
| Programmable Hybrid Embedded Controller Architecture using Clock Gating Technique KB T Subhashini, M Kamaraju IFERP International Conference 1 (1), 55-59, 2016 | | 2016 |
| Programmable core processor using data driven clock gating KB T Subhashini, M Kamaraju International Journal for Modern Trends in Science and Technology(IJMTST), 1 …, 2016 | | 2016 |
| Power efficient convolution using modulo multipliers MK T Subhashini International Journal of Applied Engineering and Research 10 (21), 42581-42587, 2015 | | 2015 |
