| Transparent trace-based binary acceleration for reconfigurable HW/SW systems J Bispo, N Paulino, JMP Cardoso, JC Ferreira IEEE Transactions on Industrial Informatics 9 (3), 1625-1634, 2012 | 22 | 2012 |
| Generation of customized accelerators for loop pipelining of binary instruction traces NMC Paulino, JC Ferreira, JMP Cardoso IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (1), 21-34, 2016 | 20 | 2016 |
| Improving performance and energy consumption in embedded systems via binary acceleration: A survey N Paulino, JC Ferreira, JMP Cardoso ACM Computing Surveys (CSUR) 53 (1), 1-36, 2020 | 18 | 2020 |
| Transparent runtime migration of loop-based traces of processor instructions to reconfigurable processing units J Bispo, N Paulino, JMP Cardoso, JC Ferreira International Journal of Reconfigurable Computing 2013, 2013 | 16 | 2013 |
| From instruction traces to specialized reconfigurable arrays J Bispo, N Paulino, JMP Cardoso, JC Ferreira 2011 International Conference on Reconfigurable Computing and FPGAs, 386-391, 2011 | 16 | 2011 |
| Transparent acceleration of program execution using reconfigurable hardware N Paulino, JC Ferreira, J Bispo, JMP Cardoso 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015 | 15 | 2015 |
| Optimizing opencl code for performance on fpga: k-means case study with integer data sets N Paulino, JC Ferreira, JMP Cardoso IEEE Access 8, 152286-152304, 2020 | 13 | 2020 |
| Self-localization via circular bluetooth 5.1 antenna array receiver N Paulino, LM Pessoa IEEE Access 11, 365-395, 2022 | 9 | 2022 |
| Design and experimental evaluation of a Bluetooth 5.1 antenna array for angle-of-arrival estimation N Paulino, LM Pessoa, A Branquinho, E Gonçalves 2022 13th International Symposium on Communication Systems, Networks and …, 2022 | 8 | 2022 |
| Dynamic partial reconfiguration of customized single-row accelerators NMC Paulino, JC Ferreira, JMP Cardoso IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (1), 116-125, 2018 | 8 | 2018 |
| Evaluating a novel Bluetooth 5.1 AoA approach for low-cost indoor vehicle tracking via simulation N Paulino, LM Pessoa, A Branquinho, E Gonçalves 2021 Joint European Conference on Networks and Communications & 6G Summit …, 2021 | 7 | 2021 |
| A reconfigurable architecture for binary acceleration of loops with memory accesses N Paulino, JC Ferreira, JMP Cardoso ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7 (4), 1-20, 2014 | 7 | 2014 |
| Trace-based reconfigurable acceleration with data cache and external memory support NMC Paulino, JC Ferreira, JMP Cardoso 2014 IEEE International Symposium on Parallel and Distributed Processing …, 2014 | 7 | 2014 |
| Architecture for transparent binary acceleration of loops with memory accesses N Paulino, JC Ferreira, JMP Cardoso Reconfigurable Computing: Architectures, Tools and Applications: 9th …, 2013 | 5 | 2013 |
| Optimizing Packet Reception Rates for Low Duty-Cycle BLE Relay Nodes N Paulino, LM Pessoa, A Branquinho, R Almeida, I Ferreira IEEE Sensors Journal 22 (13), 13753-13762, 2022 | 4 | 2022 |
| A flexible hls hoeffding tree implementation for runtime learning on fpga LM Sousa, N Paulino, JC Ferreira, J Bispo 2022 IEEE 21st Mediterranean Electrotechnical Conference (MELECON), 972-977, 2022 | 3 | 2022 |
| A Binary Translation Framework for Automated Hardware Generation N Paulino, J Bispo, JC Ferreira, JMP Cardoso IEEE Micro 41 (4), 15-23, 2021 | 3 | 2021 |
| Building Beyond HLS: Graph Analysis and Others PF Silva, J Bispo, N Paulino arXiv preprint arXiv:2104.02676, 2021 | 3 | 2021 |
| Infrared fire alarm for vehicle protection J Curva, M Lourenço, N Paulino, JP Oliveira, L Oliveira, H Oliveira 2020 International Young Engineers Forum (YEF-ECE), 19-24, 2020 | 3 | 2020 |
| On coding techniques for targeting FPGAs via OpenCL N Paulino, L Reis, JMP Cardoso Parallel Computing is Everywhere, 652-663, 2018 | 3 | 2018 |
João Canas FerreiraINESC TEC and University of PortoVerifierad e-postadress på fe.up.pt
