Robert Wille
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RevLib: An online resource for reversible functions and reversible circuits
R Wille, D Große, L Teuber, GW Dueck, R Drechsler
38th International Symposium on Multiple Valued Logic (ismvl 2008), 220-225, 2008
3222008
BDD-based synthesis of reversible logic for large functions
R Wille, R Drechsler
Proceedings of the 46th Annual Design Automation Conference, 270-275, 2009
3182009
Exact multiple-control toffoli network synthesis with SAT techniques
D Große, R Wille, GW Dueck, R Drechsler
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2009
223*2009
Verifying UML/OCL models using Boolean satisfiability
M Soeken, R Wille, M Kuhlmann, M Gogolla, R Drechsler
Proceedings of the Conference on Design, Automation and Test in Europe, 1341 …, 2010
1492010
Synthesis of quantum circuits for linear nearest neighbor architectures
M Saeedi, R Wille, R Drechsler
Quantum Information Processing 10 (3), 355-377, 2011
1222011
Elementary quantum gate realizations for multiple-control Toffoli gates
DM Miller, R Wille, Z Sasanian
2011 41st IEEE International Symposium on Multiple-Valued Logic, 288-293, 2011
1222011
Towards a design flow for reversible logic
R Wille, R Drechsler
Springer Science & Business Media, 2010
1042010
Synthesis of reversible circuits with minimal lines for large functions
M Soeken, R Wille, C Hilken, N Przigoda, R Drechsler
17th Asia and South Pacific Design Automation Conference, 85-92, 2012
1002012
RevKit: A Toolkit for Reversible Circuit Design.
M Soeken, S Frehse, R Wille, R Drechsler
Multiple-Valued Logic and Soft Computing 18 (1), 55-65, 2012
982012
Equivalence checking of reversible circuits
R Wille, D Große, DM Miller, R Drechsler
2009 39th International Symposium on Multiple-Valued Logic, 324-330, 2009
802009
Assisted behavior driven development using natural language processing
M Soeken, R Wille, R Drechsler
International Conference on Modelling Techniques and Tools for Computer …, 2012
772012
Reducing reversible circuit cost by adding lines
DM Miller, R Wille, R Drechsler
2010 40th IEEE International Symposium on Multiple-Valued Logic, 217-222, 2010
762010
An efficient methodology for mapping quantum circuits to the IBM QX architectures
A Zulehner, A Paler, R Wille
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
75*2018
Verifying dynamic aspects of UML models
M Soeken, R Wille, R Drechsler
2011 Design, Automation & Test in Europe, 1-6, 2011
682011
RevKit: An open source toolkit for the design of reversible circuits
M Soeken, S Frehse, R Wille, R Drechsler
International Workshop on Reversible Computation, 64-76, 2011
652011
Automatic design of low-power encoders using reversible circuit synthesis
R Wille, R Drechsler, C Osewold, A Garcia-Ortiz
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2012
632012
SyReC: A programming language for synthesis of reversible circuits
R Wille, S Offermann, R Drechsler
2010 Forum on Specification & Design Languages (FDL 2010), 1-6, 2010
622010
Reducing the number of lines in reversible circuits
R Wille, M Soeken, R Drechsler
Design Automation Conference, 647-652, 2010
612010
Exact one-pass synthesis of digital microfluidic biochips
O Keszocze, R Wille, TY Ho, R Drechsler
Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014
572014
Encoding OCL data types for SAT-based verification of UML/OCL models
M Soeken, R Wille, R Drechsler
International Conference on Tests and Proofs, 152-170, 2011
572011
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