Variation-tolerant architectures for convolutional neural networks in the near threshold voltage regime Y Lin, S Zhang, NR Shanbhag 2016 IEEE international workshop on signal processing systems (SiPS), 17-22, 2016 | 37 | 2016 |
Minimum precision requirements for the SVM-SGD learning algorithm C Sakr, A Patil, S Zhang, Y Kim, N Shanbhag 2017 IEEE International Conference on Acoustics, Speech and Signal …, 2017 | 24 | 2017 |
Embedded Algorithmic Noise-Tolerance for Signal Processing and Machine Learning Systems via Data Path Decomposition S Zhang, NR Shanbhag IEEE Transactions on Signal Processing 64 (13), 3338-3350, 2016 | 24 | 2016 |
Probabilistic error models for machine learning kernels implemented on stochastic nanoscale fabrics S Zhang, NR Shanbhag 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 481-486, 2016 | 9 | 2016 |
A 0.79 pJ/K-Gate, 83% Efficient Unified Core and Voltage Regulator Architecture for Sub/Near-Threshold Operation in 130 nm CMOS S Zhang, JS Tu, NR Shanbhag, PT Krein IEEE Journal of Solid-State Circuits 49 (11), 2644-2657, 2014 | 8 | 2014 |
Design of a universal robot system for health monitoring and medical services Z Sai, D Haiqiang, D Hongwei, J Zhao-Hui Zhongguo yi liao qi xie za zhi= Chinese journal of medical instrumentation …, 2010 | 7 | 2010 |
Understanding the Energy and Precision Requirements for Online Learning C Sakr, A Patil, S Zhang, Y Kim, N Shanbhag arXiv preprint arXiv:1607.00669, 2016 | 6 | 2016 |
Embedded error compensation for energy efficient DSP systems S Zhang, NR Shanbhag 2014 IEEE Global Conference on Signal and Information Processing (GlobalSIP …, 2014 | 6 | 2014 |
Reduced overhead error compensation for energy efficient machine learning kernels S Zhang, NR Shanbhag 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 15-21, 2015 | 5 | 2015 |
Error correction code management of write-once memory codes S Zhang, Y Zhu, C Bittlestone, S Ramaswamy US Patent 9,772,899, 2017 | 4 | 2017 |
Dual-mode error-correction code/write-once memory codec S Zhang, Y Zhu, C Bittlestone, S Ramaswamy US Patent 9,690,517, 2017 | 4 | 2017 |
System-Level Optimization of Switched-Capacitor VRM and Core for Sub/Near- Computing S Zhang, NR Shanbhag, PT Krein IEEE Transactions on Circuits and Systems II: Express Briefs 61 (9), 726-730, 2014 | 4 | 2014 |
Reducing the Energy Cost of Inference via In-sensor Information Processing S Zhang, M Kang, C Sakr, N Shanbhag arXiv preprint arXiv:1607.00667, 2016 | 3 | 2016 |
Dual-mode error-correction code/write-once memory codec S Zhang, Y Zhu, C Bittlestone, S Ramaswamy US Patent 10,592,333, 2020 | 1 | 2020 |
A Rank Decomposed Statistical Error Compensation Technique for Robust Convolutional Neural Networks in the Near Threshold Voltage Regime Y Lin, S Zhang, NR Shanbhag Journal of Signal Processing Systems 90 (10), 1439-1451, 2018 | 1 | 2018 |
Error-Resilient Machine Learning in Near Threshold Voltage via Classifier Ensemble S Zhang, N Shanbhag arXiv preprint arXiv:1607.07804, 2016 | 1 | 2016 |
Error correction code management of write-once memory codes S Zhang, Y Zhu, C Bittlestone, S Ramaswamy US Patent 10,191,801, 2019 | | 2019 |
Methods and apparatus to detect and correct errors in destructive read non-volatile memory Y Zhu, M Goel, S Zhang US Patent App. 16/122,575, 2019 | | 2019 |
Semiconductor memory cell multi-write avoidance encoding apparatus, systems and methods Y Zhu, M Goel, C Bittlestone, Y Qiu, S Zhang US Patent 9,715,943, 2017 | | 2017 |
Methods and apparatus to detect and correct errors in destructive read non-volatile memory Y Zhu, M Goel, S Zhang US Patent App. 14/989,293, 2017 | | 2017 |