| Razor: A low-power pipeline based on circuit-level timing speculation D Ernst, NS Kim, S Das, S Pant, R Rao, T Pham, C Ziesler, D Blaauw, ... Proceedings. 36th Annual IEEE/ACM International Symposium on …, 2003 | 1810 | 2003 |
| Leakage current: Moore's law meets static power NS Kim, T Austin, D Blaauw, T Mudge, JS Hu, MJ Irwin, M Kandemir, ... computer, 68-75, 2003 | 1688 | 2003 |
| Drowsy caches: simple techniques for reducing leakage power K Flautner, NS Kim, S Martin, D Blaauw, T Mudge ACM SIGARCH Computer architecture news 30 (2), 148-157, 2002 | 1223 | 2002 |
| GPUWattch: Enabling energy optimizations in GPGPUs J Leng, T Hetherington, A ElTantawy, S Gilani, NS Kim, TM Aamodt, ... International Symposium on Computer Architecture, 487-498, 2013 | 713 | 2013 |
| Approximate computing: A survey Q Xu, T Mytkowicz, NS Kim IEEE Design & Test 33 (1), 8-22, 2015 | 534 | 2015 |
| Razor: circuit-level correction of timing errors for low-power operation D Ernst, S Das, S Lee, D Blaauw, T Austin, T Mudge, NS Kim, K Flautner IEEE Micro 24 (6), 10-20, 2004 | 521 | 2004 |
| Energy-efficient and metastability-immune resilient circuits for dynamic variation tolerance KA Bowman, JW Tschanz, NS Kim, JC Lee, CB Wilkerson, SLL Lu, ... IEEE Journal of Solid-State Circuits 44 (1), 49-63, 2008 | 430 | 2008 |
| NDA: Near-DRAM acceleration architecture leveraging commodity DRAM devices and standard memory modules A Farmahini-Farahani, JH Ahn, K Morrow, NS Kim 2015 IEEE 21st International Symposium on High Performance Computer …, 2015 | 301 | 2015 |
| Adaptive frequency and biasing techniques for tolerance to dynamic temperature-voltage variations and aging J Tschanz, NS Kim, S Dighe, J Howard, G Ruhl, S Vangal, S Narendra, ... 2007 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2007 | 271 | 2007 |
| Circuit and microarchitectural techniques for reducing cache leakage power NS Kim, K Flautner, D Blaauw, T Mudge IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12 (2), 167-184, 2004 | 271 | 2004 |
| Drowsy instruction caches. leakage power reduction using dynamic voltage scaling and cache sub-bank prediction NS Kim, K Flautner, D Blaauw, T Mudge 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002 …, 2002 | 246 | 2002 |
| The case for GPGPU spatial multitasking JT Adriaens, K Compton, NS Kim, MJ Schulte IEEE International Symposium on High-Performance Comp Architecture, 1-12, 2012 | 242 | 2012 |
| Energy-efficient approximate multiplication for digital signal processing and classification applications S Narayanamoorthy, HA Moghaddam, Z Liu, T Park, NS Kim IEEE transactions on very large scale integration (VLSI) systems 23 (6 …, 2014 | 230 | 2014 |
| Yield-driven near-threshold SRAM design G Chen, D Sylvester, D Blaauw, T Mudge, NS Kim Proceedings of the 2007 IEEE/ACM international conference on Computer-aided …, 2007 | 215 | 2007 |
| Chameleon: Versatile and practical near-DRAM acceleration architecture for large memory systems H Asghari-Moghaddam, YH Son, JH Ahn, NS Kim 2016 49th annual IEEE/ACM international symposium on Microarchitecture …, 2016 | 139 | 2016 |
| Wordline & bitline pulsing schemes for improving SRAM cell stability in low-Vcc 65nm CMOS designs M Khellah, Y Ye, N Kim, D Somasekhar, G Pandya, A Farhang, K Zhang, ... 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers., 9-10, 2006 | 131 | 2006 |
| VARIUS-NTV: A microarchitectural model to capture the increased sensitivity of manycores to process variations at near-threshold voltages UR Karpuzcu, KB Kolluru, NS Kim, J Torrellas IEEE/IFIP International Conference on Dependable Systems and Networks (DSN …, 2012 | 117 | 2012 |
| Optimizing throughput of power-and thermal-constrained multicore processors using DVFS and per-core power-gating J Lee, NS Kim Design Automation Conference, 2009. DAC'09. 46th ACM/IEEE, 47-50, 2009 | 112 | 2009 |
| Improving throughput of power-constrained GPUs using dynamic voltage/frequency and core scaling J Lee, V Sathisha, M Schulte, K Compton, NS Kim 2011 International Conference on Parallel Architectures and Compilation …, 2011 | 111 | 2011 |
| Lossless and lossy memory I/O link compression for improving performance of GPGPU workloads V Sathish, MJ Schulte, NS Kim Proceedings of the 21st international conference on Parallel architectures …, 2012 | 108 | 2012 |
Trevor MudgeBredt Family Professor of Engineering, University of MichiganVerified email at eecs.umich.edu
