| Surface charge density of unpassivated and passivated metal-catalyzed silicon nanowires K Seo, S Sharma, AA Yasseri, DR Stewart, TI Kamins Electrochemical and solid-state letters 9 (3), G69, 2006 | 147 | 2006 |
| A 10nm Platform Technology for Low Power and High Performance Application Featuring FINFET Devices with Multi Workfunction Gate Stack on Bulk and SOI Symp. VLSI Tech. Digest,, pp 14-15, 2014 | 109* | 2014 |
| Highly manufacturable 7nm FinFET technology featuring EUV lithography for low power and high performance applications D Ha, C Yang, J Lee, S Lee, SH Lee, KI Seo, HS Oh, EC Hwang, SW Do, ... 2017 Symposium on VLSI Technology, T68-T69, 2017 | 76 | 2017 |
| Improvement in High-k (HfO2/SiO2) Reliability by Incorporation of Fluorine K Seo, R Sreenivasan, PC McIntyre, KC Saraswat Electron Device Letters, IEEE 27 (10), 821-823, 2006 | 72* | 2006 |
| Novel stress-memorization-technology (SMT) for high electron mobility enhancement of gate last high-k/metal gate devices KY Lim, H Lee, C Ryu, KI Seo, U Kwon, S Kim, J Choi, K Oh, HK Jeon, ... 2010 International Electron Devices Meeting, 10.1. 1-10.1. 4, 2010 | 71 | 2010 |
| Chemical states and electronic structure of a HfO2/ Ge(001) interface K Seo, PC McIntyre, S Sun, DI Lee, P Pianetta, KC Saraswat Applied Physics Letters 87 (4), 042902-042902-3, 2005 | 62 | 2005 |
| Chemical states and electrical properties of a high-k metal oxide/silicon interface with oxygen-gettering titanium-metal-overlayer KI Seo, DI Lee, P Pianetta, H Kim, KC Saraswat, PC McIntyre Applied physics letters 89 (14), 142912-142912-3, 2006 | 49 | 2006 |
| Formation of an interfacial Zr-silicate layer between ZrO2 and Si through in situ vacuum annealing K Seo, PC McIntyre, H Kim, KC Saraswat Applied Physics Letters 86 (8), 2005 | 42 | 2005 |
| Semiconductor device and fabricating method thereof S Suk, K Seo US Patent 9,613,871, 2017 | 35 | 2017 |
| Bottom oxidation through STI (BOTS)—A novel approach to fabricate dielectric isolated FinFETs on bulk substrates K Cheng, S Seo, J Faltermeier, D Lu, T Standaert, I Ok, A Khakifirooz, ... 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical …, 2014 | 35 | 2014 |
| Vertical-transport nanosheet technology for CMOS scaling beyond lateral-transport devices H Jagannathan, B Anderson, CW Sohn, G Tsutsui, J Strane, R Xie, S Fan, ... 2021 IEEE International Electron Devices Meeting (IEDM), 26.1. 1-26.1. 4, 2021 | 31 | 2021 |
| A novel tensile Si (n) and compressive SiGe (p) dual-channel CMOS FinFET co-integration scheme for 5nm logic applications and beyond D Bae, G Bae, KK Bhuwalka, SH Lee, MG Song, T Jeon, C Kim, W Kim, ... 2016 IEEE International Electron Devices Meeting (IEDM), 28.1. 1-28.1. 4, 2016 | 30 | 2016 |
| Semiconductor device having nanowire channel DK Kim, K Seo US Patent 9,590,038, 2017 | 28 | 2017 |
| Random telegraph noise in n-type and p-type silicon nanowire transistors S Yang, KH Yeo, DW Kim, K Seo, D Park, G Jin, KS Oh, H Shin 2008 IEEE International Electron Devices Meeting, 1-4, 2008 | 24 | 2008 |
| Fluorine incorporation at HfO2∕ SiO2 interfaces in high-k metal-oxide-semiconductor gate stacks: Local electronic structure JH Ha, K Seo, PC McIntyre, KC Sarawat, K Cho Applied physics letters 90 (11), 2007 | 24 | 2007 |
| CInterface Layers for High-k/Ge Gate Stacks: Are They Necessary? P.l McIntyre, D.Chi, C. O. Chui, H. Kim, K-I Seo ECS Trans 3, 519, 2006 | 21 | 2006 |
| Semiconductor device having nanowire DK Kim, K Seo US Patent 9,755,034, 2017 | 17 | 2017 |
| Semiconductor device having fin-type field effect transistor and method of manufacturing the same D Bae, K Seo US Patent 9,735,153, 2017 | 15 | 2017 |
| Semiconductor device having a gate all around structure and a method for fabricating the same SD Suk, KIM Bom-Soo, K Seo US Patent 9,679,965, 2017 | 14 | 2017 |
| Semiconductor device having gate-all-around transistor and method of manufacturing the same D Bae, K Seo US Patent 9,443,978, 2016 | 13 | 2016 |
