Andrew Waterman
Andrew Waterman
Verifierad e-postadress på eecs.berkeley.edu
TitelCiteras avÅr
Roofline: An insightful visual performance model for floating-point programs and multicore architectures
S Williams, A Waterman, D Patterson
Communications of the Association for Computing Machinery, 2009
14222009
Single-chip microprocessor that communicates directly using light
C Sun, MT Wade, Y Lee, JS Orcutt, L Alloatti, MS Georgas, AS Waterman, ...
Nature 528 (7583), 534, 2015
5662015
Chisel: constructing hardware in a scala embedded language
J Bachrach, H Vo, B Richards, Y Lee, A Waterman, R Avižienis, ...
DAC Design Automation Conference 2012, 1212-1221, 2012
3692012
Proving program termination
B Cook, A Podelski, A Rybalchenko
Communications of the ACM 54 (5), 88-98, 2011
171*2011
The rocket chip generator
K Asanovic, R Avizienis, J Bachrach, S Beamer, D Biancolin, C Celio, ...
EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2016-17, 2016
1312016
RAMP gold: an FPGA-based architecture simulator for multiprocessors
Z Tan, A Waterman, R Avizienis, Y Lee, H Cook, D Patterson, K Asanović
Proceedings of the 47th Design Automation Conference, 463-468, 2010
1242010
A 45nm 1.3 GHz 16.7 double-precision GFLOPS/W RISC-V processor with vector accelerators
Y Lee, A Waterman, R Avizienis, H Cook, C Sun, V Stojanović, K Asanović
ESSCIRC 2014-40th European Solid State Circuits Conference (ESSCIRC), 199-202, 2014
832014
The RISC-V instruction set manual, volume I: User-level ISA
A Waterman, Y Lee, DA Patterson, K Asanovic
CS Division, EECE Department, University of California, Berkeley, 2014
812014
A case for FAME: FPGA architecture model execution
Z Tan, A Waterman, H Cook, S Bird, K Asanović, D Patterson
ACM SIGARCH Computer Architecture News 38 (3), 290-301, 2010
772010
The risc-v instruction set manual, volume i: Base user-level isa
A Waterman, Y Lee, DA Patterson, K Asanovic
EECS Department, UC Berkeley, Tech. Rep. UCB/EECS-2011-62 116, 2011
722011
The RISC-V Instruction Set Manual. Volume 1: User-Level ISA, Version 2.0
A Waterman, Y Lee, DA Patterson, K Asanovi
CALIFORNIA UNIV BERKELEY DEPT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES, 2014
702014
Processes and resource management in a scalable many-core OS
K Klues, B Rhoden, Y Zhu, A Waterman, E Brewer
HotPar10, Berkeley, CA, 2010
402010
An agile approach to building RISC-V microprocessors
Y Lee, A Waterman, H Cook, B Zimmer, B Keller, A Puggelli, J Kwak, ...
IEEE Micro 36 (2), 8-20, 2016
382016
A RISC-V vector processor with simultaneous-switching switched-capacitor DC–DC converters in 28 nm FDSOI
B Zimmer, Y Lee, A Puggelli, J Kwak, R Jevtić, B Keller, S Bailey, ...
IEEE Journal of Solid-State Circuits 51 (4), 930-942, 2016
372016
The risc-v instruction set manual volume 2: Privileged architecture version 1.7
A Waterman, Y Lee, R Avizienis, DA Patterson, K Asanovic
University of California at Berkeley Berkeley United States, 2015
362015
A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI
B Zimmer, Y Lee, A Puggelli, J Kwak, R Jevtic, B Keller, S Bailey, ...
2015 Symposium on VLSI Circuits (VLSI Circuits), C316-C317, 2015
322015
The risc-v instruction set manual
A Waterman, Y Lee, D Patterson, K Asanovic
volume I: User-level ISA, version 2.0, EECS Department, University of …, 2014
322014
Design of the RISC-V instruction set architecture
AS Waterman
UC Berkeley, 2016
252016
A case for os-friendly hardware accelerators
H Vo, Y Lee, A Waterman, K Asanovic
Workshop on the Interaction between Operating System and Computer …, 2013
172013
Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking
Y Lee, B Zimmer, A Waterman, A Puggelli, J Kwak, R Jevtic, B Keller, ...
2015 IEEE Hot Chips 27 Symposium (HCS), 1-45, 2015
122015
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Artiklar 1–20