| Electrical transport in solids KC Kao, W Hwang, SI Choi Physics Today 36 (10), 90-90, 1983 | 1800 | 1983 |
| Merged logic and memory combining thin film and bulk Si transistors PG Emmma, W Hwang, SM Gates US Patent 6,620,659, 2003 | 343 | 2003 |
| Method of fabricating cross-point lightly-doped drain-source trench transistor SH Dhong, W Hwang, NC Lu US Patent 5,021,355, 1991 | 179 | 1991 |
| Topics in the optimization of millimeter-wave mixers PH Siegel, AR Kerr, W Hwang | 145 | 1984 |
| Stacked bit-line architecture for high density cross-point memory cell array CM Chu, SH Dhong, W Hwang, NCC Lu US Patent 5,107,459, 1992 | 131 | 1992 |
| System-on-chip layout compilation WK Luk, W Hwang, Y Katayama US Patent 5,883,814, 1999 | 117 | 1999 |
| Design and implementation of differential cascode voltage switch with pass-gate (DCVSPG) logic for high-performance digital systems F Lai, W Hwang IEEE journal of solid-state circuits 32 (4), 563-573, 1997 | 117 | 1997 |
| A 65 nm 0.165 fJ/Bit/Search 256144 TCAM Macro Design for IPv6 Lookup Tables PT Huang, W Hwang IEEE Journal of Solid-State Circuits 46 (2), 507-519, 2010 | 107 | 2010 |
| Design and Iso-Area Analysis of 9T Subthreshold SRAM With Bit-Interleaving Scheme in 65-nm CMOS MH Chang, YT Chiu, W Hwang IEEE Transactions on Circuits and Systems II: Express Briefs 59 (7), 429-433, 2012 | 101 | 2012 |
| Novel Cu-to-Cu Bonding With Ti Passivation at 180 in 3-D Integration YP Huang, YS Chien, RN Tzeng, MS Shy, TH Lin, KH Chen, CT Chiu, ... IEEE Electron Device Letters 34 (12), 1551-1553, 2013 | 97 | 2013 |
| Cross-point lightly-doped drain-source trench transistor and fabrication process therefor SH Dhong, W Hwang, NCC Lu US Patent 4,954,854, 1990 | 90 | 1990 |
| Integrated trench-transistor structure and fabrication process B Davari, W Hwang, NC Lu US Patent 4,881,105, 1989 | 90 | 1989 |
| Folded bitline, ultra-high density dynamic random access memory having access transistors stacked above trench storage capacitors SH Dhong, W Hwang, LM Terman, MR Wordeman US Patent 5,214,603, 1993 | 88 | 1993 |
| Impacts of NBTI/PBTI on timing control circuits and degradation tolerant design in nanoscale CMOS SRAM HI Yang, SC Yang, W Hwang, CT Chuang IEEE Transactions on Circuits and Systems I: Regular Papers 58 (6), 1239-1251, 2011 | 86 | 2011 |
| A 45nm dual-port SRAM with write and read capability enhancement at low voltage DP Wang, HJ Liao, H Yamauchi, YH Chen, YL Lin, SH Lin, DC Liu, ... 2007 IEEE International SOC Conference, 211-214, 2007 | 85 | 2007 |
| Merged logic and memory combining thin film and bulk Si transistors PG Emma, W Hwang, SMC Gates US Patent 6,271,542, 2001 | 83 | 2001 |
| System integration of DRAM macros and logic cores in a single chip architecture WK Luk, W Hwang US Patent 5,790,839, 1998 | 83 | 1998 |
| High density memory cell structure having a vertical trench transistor self-aligned with a vertical trench capacitor and fabrication methods therefor W Hwang, NC Lu US Patent 4,833,516, 1989 | 74 | 1989 |
| A 500-MHz, 32-word/spl times/64-bit, eight-port self-resetting CMOS register file W Hwang, RV Joshi, WH Henkels IEEE Journal of Solid-State Circuits 34 (1), 56-67, 1999 | 70 | 1999 |
| Method and system for selecting sizes of components for integrated circuits GD Gristede, W Hwang, CR Tretz US Patent 6,175,949, 2001 | 69 | 2001 |
Kuan-Neng ChenDepartment of Electronics Engineering, National Yang Ming Chiao Tung UniversityVerified email at mail.nctu.edu.tw
