| T-count optimized quantum circuit designs for single-precision floating-point division SS Gayathri, R Kumar, S Dhanalakshmi, G Dooly, DB Duraibabu Electronics 10 (6), 703, 2021 | 23 | 2021 |
| T-count optimized wallace tree integer multiplier for quantum computing SS Gayathri, R Kumar, S Dhanalakshmi, BK Kaushik, M Haghparast International Journal of Theoretical Physics 60 (8), 2823-2835, 2021 | 8 | 2021 |
| Design and implementation of efficient reversible even parity checker and generator SS Gayathri, AV Ananthalakshmi 2014 International Conference on Science Engineering and Management Research …, 2014 | 7 | 2014 |
| A novel and efficient square root computation quantum circuit for floating-point standard R Kumar, M Haghparast, S Dhanalakshmi International Journal of Theoretical Physics 61 (9), 1-15, 2022 | 2 | 2022 |
| T-count optimized quantum circuit for floating point addition and multiplication SS Gayathri, R Kumar, S Dhanalakshmi, BK Kaushik Quantum Information Processing 20 (11), 378, 2021 | 2 | 2021 |
| Efficient Floating-point Division Quantum Circuit using Newton-Raphson Division SS Gayathri, R Kumar, S Dhanalakshmi Journal of Physics: Conference Series 2335 (1), 012058, 2022 | 1 | 2022 |
| Multi-Pedestrian Detection using Hybrid ML Algorithms for Autonomous Vehicles S Mukherjee, T Sharma, A Singh, SS Gayathri, S Dhanalakshmi 2023 International Conference on Recent Advances in Science and Engineering …, 2023 | | 2023 |
| Quantum Information Processing: A Review on Quantum Arithmetic Circuits DS S. S. Gayathri, R. Kumar International Journal of Advanced Science and Technology 29 (3), 2020 | | 2020 |
| Design and implementation of pipelined AES on FPGA G Kalpana Priyanka ICASISET, 2018 | | 2018 |
| RAILWAY CONDITION MONITORING USING WIRELESS ZIGBEE NODES BA S.S.Gayathri , Atharva Vitekar , Karthik Padmanabhan International Journal of Pure and Applied Mathematics 118 (10), 2018 | | 2018 |
| Realization of higher order reconfigurable block FIR filter for hearing aid applications GSS Someshwara rao ICRTCIT,SRM University, 2017 | | 2017 |
| Efficient Reversible GVJ Gate as Half Adder & Full Adder and its Testing on Single Precision Floating Point Multiplier SS Gayathri International journal of control theory and applications 10, 189-196, 2017 | | 2017 |
| Reversible SSG Gate for Implementing Parity Checker Generator andMagnitude Comparator SS Gayathri, R Dayana, P Malarvezhi Indian Journal of Science and Technology 9, 20, 2016 | | 2016 |
