Yuan Lu
Title
Cited by
Cited by
Year
Counterexample-guided abstraction refinement
E Clarke, O Grumberg, S Jha, Y Lu, H Veith
International Conference on Computer Aided Verification, 154-169, 2000
22942000
Counterexample-guided abstraction refinement for symbolic model checking
E Clarke, O Grumberg, S Jha, Y Lu, H Veith
Journal of the ACM (JACM) 50 (5), 752-794, 2003
11202003
Progress on the state explosion problem in model checking
E Clarke, O Grumberg, S Jha, Y Lu, H Veith
Informatics, 176-194, 2001
3072001
Tree-like counterexamples in model checking
E Clarke, S Jha, Y Lu, H Veith
Proceedings 17th Annual IEEE Symposium on Logic in Computer Science, 19-29, 2002
1872002
Temporal logic for scenario-based specifications
H Kugler, D Harel, A Pnueli, Y Lu, Y Bontemps
International Conference on Tools and Algorithms for the Construction and …, 2005
1322005
Verifying IP-core based system-on-chip designs
P Chauhan, EM Clarke, Y Lu, D Wang
Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No. 99TH8454), 27-31, 1999
911999
Embedded tutorial: Formal equivalence checking between system-level models and RTL
A Koelbl, Y Lu, A Mathur
ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005 …, 2005
322005
Equivalence checking using abstract BDDs
S Jha, Y Lu, M Minea, EM Clarke
Proceedings International Conference on Computer Design VLSI in Computers …, 1997
311997
Executable protocol specification in ESL
E Clarke, S German, Y Lu, H Veith, D Wang
International Conference on Formal Methods in Computer-Aided Design, 217-236, 2000
262000
Abstract BDDs: a technique for using abstraction in model checking
E Clarke, S Jha, Y Lu, D Wang
Advanced Research Working Conference on Correct Hardware Design and …, 1999
231999
OBDD variable ordering using sampling based schemes
J Jain, Y Lu
US Patent 6,389,374, 2002
202002
Efficient variable ordering using aBDD based sampling
Y Lu, J Jain, E Clarke, M Fujita
Proceedings of the 37th Annual Design Automation Conference, 687-692, 2000
202000
Automatic abstraction in model checking
Y Lu
Carnegie Mellon University, 2000
192000
Design verification using formal techniques
Y Lu
US Patent App. 10/835,561, 2005
172005
Synchronization of large sequential circuits by partial reset
Y Lu, I Pomeranz
Proceedings of 14th VLSI Test Symposium, 93-98, 1996
161996
A semi-formal verification methodology
Y Lu, W Li
ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No …, 2001
152001
Methods for automatically generating assertions
Y Lu, Y Zhu
US Patent 7,926,020, 2011
132011
Temporal logic for live sequence charts
H Kugler, D Harel, A Pnueli, Y Lu, Y Bontemps
Proc. of Tools and Algorithms for Construction and Analysis of Systems …, 2000
132000
Analysis of composition complexity and how to obtain smaller canonical graphs
J Jain, K Mohanram, D Moundanos, I Wegener, Y Lu
Proceedings of the 37th Annual Design Automation Conference, 681-686, 2000
102000
Systems and methods for generating predicates and assertions
Y Lu, Y Zhu
US Patent 8,326,778, 2012
82012
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Articles 1–20