| Experimental demonstration of capacitorless A2RAM cells on silicon-on-insulator N Rodriguez, C Navarro, F Gamiz, F Andrieu, O Faynot, S Cristoloveanu IEEE Electron Device Letters 33 (12), 1717-1719, 2012 | 47 | 2012 |
| Extended Analysis of the -FET: Operation as Capacitorless eDRAM C Navarro, J Lacord, MS Parihar, F Adamu-Lema, M Duan, N Rodriguez, ... IEEE Transactions on Electron Devices 64 (11), 4486-4491, 2017 | 27 | 2017 |
| Supercoupling effect in short-channel ultrathin fully depleted silicon-on-insulator transistors C Navarro, M Bawedin, F Andrieu, B Sagnes, F Martinez, S Cristoloveanu Journal of Applied Physics 118 (18), 184504, 2015 | 27 | 2015 |
| A review of the Z2-FET 1T-DRAM memory: Operation mechanisms and key parameters S Cristoloveanu, KH Lee, MS Parihar, H El Dirani, J Lacord, S Martinie, ... Solid-State Electronics 143, 10-19, 2018 | 25 | 2018 |
| -FET as Capacitor-Less eDRAM Cell For High-Density Integration C Navarro, M Duan, MS Parihar, F Adamu-Lema, S Coseman, J Lacord, ... IEEE Transactions on Electron Devices 64 (12), 4904-4909, 2017 | 22 | 2017 |
| Experimental Demonstration of Operational Z2-FET Memory Matrix S Navarro, C Navarro, C Marquez, H El Dirani, P Galy, M Bawedin, ... IEEE Electron Device Letters 39 (5), 660-663, 2018 | 16 | 2018 |
| Multibranch mobility analysis for the characterization of FDSOI transistors C Navarro, N Rodriguez, A Ohata, F Gamiz, F Andrieu, ... IEEE electron device letters 33 (8), 1102-1104, 2012 | 15 | 2012 |
| Experimental developments of A2RAM memory cells on SOI and bulk substrates N Rodriguez, F Gamiz, C Navarro, C Marquez, F Andrieu, O Faynot, ... Solid-State Electronics 103, 7-14, 2015 | 14 | 2015 |
| Reconfigurable field effect transistor for advanced CMOS: A comparison with FDSOI devices C Navarro, S Barraud, S Martinie, J Lacord, MA Jaud, M Vinet 2016 Joint International EUROSOI Workshop and International Conference on …, 2016 | 13 | 2016 |
| Fully depleted SOI characterization by capacitance analysis of pin gated diodes C Navarro, M Bawedin, F Andrieu, J Cluzel, S Cristoloveanu IEEE Electron Device Letters 36 (1), 5-7, 2014 | 13 | 2014 |
| Impact of back-gate biasing on effective field and mobility in ultrathin silicon-on-insulator metal-oxide-semiconductor field-effect-transistors A Ohata, N Rodriguez, C Navarro, L Donetti, F Gamiz, ... Journal of Applied Physics 113 (14), 144514, 2013 | 13 | 2013 |
| Properties of 22nm node extremely-thin-SOI MOSFETs N Rodriguez, F Andrieu, C Navarro, O Faynot, F Gamiz, S Cristoloveanu IEEE 2011 International SOI Conference, 1-2, 2011 | 10 | 2011 |
| Self-heating effects in ultrathin FD SOI transistors N Rodriguez, C Navarro, F Andrieu, O Faynot, F Gamiz, S Cristoloveanu IEEE 2011 International SOI Conference, 1-2, 2011 | 10 | 2011 |
| Low-power Z2-FET capacitorless 1T-DRAM MS Parihar, KH Lee, H El Dirani, C Navarro, J Lacord, S Martinie, ... 2017 IEEE International Memory Workshop (IMW), 1-4, 2017 | 9 | 2017 |
| Overestimation of short-channel effects due to intergate coupling in advanced FD-SOI MOSFETs C Navarro, M Bawedin, F Andrieu, S Cristoloveanu IEEE Transactions on Electron Devices 61 (9), 3274-3281, 2014 | 9 | 2014 |
| Evaluation of thin-oxide Z2-FET DRAM cell S Navarro, KH Lee, C Marquez, C Navarro, M Parihar, H Park, P Galy, ... 2018 Joint International EUROSOI Workshop and International Conference on …, 2018 | 8 | 2018 |
| Thorough understanding of retention time of Z2FET memory operation M Duan, C Navarro, B Cheng, F Adamu-Lema, X Wang, VP Georgiev, ... IEEE Transactions on Electron Devices 66 (1), 383-388, 2018 | 7 | 2018 |
| Simulation based DC and dynamic behaviour characterization of Z2FET F Adamu-Lema, M Duan, C Navarro, V Georgiev, B Cheng, X Wang, ... Simulation of Semiconductor Processes and Devices (SISPAD), 2017 …, 2017 | 7 | 2017 |
| 2D-TCAD simulation on retention time of Z2FET for DRAM application M Duan, F Adam-Lema, B Cheng, C Navarro, X Wang, VP Georgiev, ... 2017 International Conference on Simulation of Semiconductor Processes and …, 2017 | 7 | 2017 |
| Reconfigurable field effect transistor for advanced CMOS: Advantages and limitations C Navarro, S Barraud, S Martinie, J Lacord, MA Jaud, M Vinet Solid-State Electronics 128, 155-162, 2017 | 7 | 2017 |
Cristoloveanu, SorinGrenoble INPVerified email at minatec.grenoble-inp.fr
