Jeong-Kyoum Kim
Jeong-Kyoum Kim
Principal Engineer, SK Hynix
Verified email at - Homepage
Cited by
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A 20-GHz phase-locked loop for 40-Gb/s serializing transmitter in 0.13-μm CMOS
J Kim, JK Kim, BJ Lee, N Kim, DK Jeong, W Kim
Solid-State Circuits, IEEE Journal of 41 (4), 899-908, 2006
Low-voltage high-performance silicon photonic devices and photonic integrated circuits operating up to 30 Gb/s
G Kim, JW Park, IG Kim, S Kim, S Kim, JM Lee, GS Park, J Joo, KS Jang, ...
Optics Express 19 (27), 26936-26947, 2011
Circuit techniques for a 40Gb/s transmitter in 0.13μm CMOS
J Kim, JK Kim, BJ Lee, MS Hwang, HR Lee, SH Lee, N Kim, DK Jeong, ...
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC …, 2005
Design Optimization of On-Chip Inductive Peaking Structures for 0.13-CMOS 40-Gb/s Transmitter Circuits
J Kim, JK Kim, BJ Lee, DK Jeong
Circuits and Systems I: Regular Papers, IEEE Transactions on 56 (12), 2544-2555, 2009
A Fully Integrated 0.13-μm CMOS 40-Gb/s Serial Link Transceiver
JK Kim, J Kim, KIM GYUDONG, DK Jeong
IEEE journal of solid-state circuits 44 (5), 1510-1521, 2009
Memory system
SHH Jeong-Kyoum Kim, Jung-hwan Choi
US Patent US 2013/0254495 A1, 2013
Stacked die package, system including the same, and method of manufacturing the same
JK Kim, JH Choi
US Patent App. 14/094,952, 2013
A 180-Mb/s to 3.2-Gb/s, continuous-rate, fast-locking CDR without using external reference clock
MS Hwang, SY Lee, JK Kim, S Kim, DK Jeong
Solid-State Circuits Conference, 2007. ASSCC'07. IEEE Asian, 144-147, 2007
Bulk-Si photonics technology for DRAM interface [Invited]
H Byun, J Bok, K Cho, K Cho, H Choi, J Choi, S Choi, S Han, S Hong, ...
Photonics Research 2 (3), A25-A33, 2014
Semiconductor Device Capable of Rescuing Defective Characteristics Occurring After Packaging
SJJ Jeong-Kyoum Kim, Seok-Hun Hyun, Jung-hwan Choi
US Patent US 20130223171 A1, 2013
Memory buffer performing error correction coding (ecc)
SJJ Jeong-Kyoum Kim, Jung Hwan Choi, Seok Hun Hyun
US Patent US 2013/0198587 A1, 2013
A 40-Gb/s transceiver in 0.13-μm CMOS technology
JK Kim, J Kim, G Kim, H Chi, DK Jeong
VLSI Circuits, 2008 IEEE Symposium on, 196-197, 2008
A 20-Gb/s full-rate 2^ 7-1 PRBS generator integrated with 20-GHz PLL in 0.13-μm CMOS
JK Kim, J Kim, DK Jeong
IEEE Asian Solid-State Circuits Conference, 2008. A-SSCC'08., 221-224, 2008
A 26.5–37.5 GHz frequency divider and a 73-GHz-BW CML buffer in 0.13 μm CMOS
JK Kim, J Kim, SY Lee, S Kim, DK Jeong
Solid-State Circuits Conference, 2007. ASSCC'07. IEEE Asian, 148-151, 2007
Memory chip package, memory system having the same and driving method thereof
JK Kim, S InDal, J Choi
US Patent App. 14/094,813, 2013
Si-based optical I/O for optical memory interface
K Ha, D Shin, H Byun, K Cho, K Na, H Ji, J Pyo, S Hong, K Lee, B Lee, ...
SPIE OPTO, 82670F-82670F-6, 2012
Memory modules and memory systems including the same
JK Kim, ID Song, J Choi
US Patent App. 14/091,385, 2013
FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects
H Byun, I Joe, S Kim, K Lee, S Hong, H Ji, J Pyo, K Cho, S Kim, S Suh, ...
10th International Conference on Group IV Photonics, 2013
A Heterogeneous Dual DLL and Quantization error minimized ZQ calibration for 30nm 1.2 V 4Gb 3.2 Gb/s/pin DDR4 SDRAM
T Na, Y Shim, I Song, JK Kim, S Hyun, JB Kim, JH Choi, CW Kim, JB Lee, ...
VLSI Circuits (VLSIC), 2013 Symposium on, C242-C243, 2013
Receiving circuit, and semiconductor device and system configured to use the receiving circuit
JK Kim, JY Song, HK Chi
US Patent App. 15/642,566, 2018
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