tiberiu seceleanu
tiberiu seceleanu
ABB Corporate Research Centre & Mälardalen University
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Cited by
Cited by
Year
Making interoperability visible: Data visualization of cyber-physical systems development tool chains
D Gürdür, J El-Khoury, T Seceleanu, L Lednicki
Journal of industrial information integration 4, 26-34, 2016
432016
Systematic design of synchronous digital circuits
T Seceleanu
Åbo Akademi University, 2001
362001
On-chip segmented bus: a self-timed approach [SOC]
T Seceleanu, J Plosila, P Lijeberg
15th Annual IEEE International ASIC/SOC Conference, 216-220, 2002
342002
Power and area efficient design of network-on-chip router through utilization of idle buffers
K Latif, T Seceleanu, H Tenhunen
2010 17th IEEE International Conference and Workshops on Engineering of …, 2010
232010
Implementation of a self-timed segmented bus
J Plosila, T Seceleanu, P Liljeberg
IEEE Design & Test of Computers 20 (6), 44-50, 2003
232003
PVS-NoC: Partial virtual channel sharing NoC architecture
K Latif, AM Rahmani, L Guang, T Seceleanu, H Tenhunen
2011 19th International Euromicro Conference on Parallel, Distributed and …, 2011
222011
The SegBus platform–architecture and communication mechanisms
T Seceleanu
Journal of Systems Architecture 53 (4), 151-169, 2007
192007
A model-based design process for the segbus distributed architecture
D Truscan, T Seceleanu, J Lilius, H Tenhunen
15th Annual IEEE International Conference and Workshop on the Engineering of …, 2008
182008
Resource allocation methodology for the segmented bus platform
T Seceleanu, V Leppanen, J Suomi, O Nevalainen
Proceedings 2005 IEEE International SOC Conference, 129-132, 2005
172005
Communication on a segmented bus
T Seceleanu
IEEE International SOC Conference, 2004. Proceedings., 205-208, 2004
162004
Partitioning decision process for embedded hardware and software deployment
G Sapienza, T Seceleanu, I Crnknovic
2013 IEEE 37th Annual Computer Software and Applications Conference …, 2013
152013
Towards a model-based approach for allocating tasks to multicore processors
J Feljan, J Carlson, T Seceleanu
2012 38th Euromicro Conference on Software Engineering and Advanced …, 2012
152012
Application development flow for on-chip distributed architectures
K Latif, M Niazi, H Tenhunen, T Seceleanu, S Sezer
2008 IEEE International SOC Conference, 163-168, 2008
152008
Complexity analysis of H. 264 decoder for FPGA design
T Lindroth, N Avessta, J Teuhola, T Seceleanu
2006 IEEE International Conference on Multimedia and Expo, 1253-1256, 2006
142006
Developing adaptive systems with synchronized architectures
T Seceleanu, D Garlan
Journal of Systems and Software 79 (11), 1514-1526, 2006
132006
A tool integration framework for sustainable embedded systems development
T Seceleanu, G Sapienza
Computer 46 (11), 68-71, 2013
122013
Improving the performance of bus platforms by means of segmentation and optimized resource allocation
T Seceleanu, V Leppänen, OS Nevalainen
EURASIP Journal on Embedded Systems 2009, 1-14, 2009
122009
Partial virtual channel sharing: a generic methodology to enhance resource management and fault tolerance in networks-on-chip
K Latif, AM Rahmani, E Nigussie, T Seceleanu, M Radetzki, H Tenhunen
Journal of electronic testing 29 (3), 431-452, 2013
112013
Multiprocessor real time edge detection using FPGA IP cores
I Nita, T Costachioiu, V Lazarescu, T Seceleanu
2011 IEEE 7th International Conference on Intelligent Computer Communication …, 2011
112011
UML-based development of embedded real-time software on multi-core in practice: lessons learned and future perspectives
F Ciccozzi, T Seceleanu, D Corcoran, D Scholle
IEEE Access 4, 6528-6540, 2016
102016
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Articles 1–20