| Symbolic model checking: 1020 states and beyond JR Burch, EM Clarke, KL McMillan, DL Dill, LJ Hwang Information and computation 98 (2), 142-170, 1992 | 4682 | 1992 |
| Symbolic model checking for sequential circuit verification JR Burch, EM Clarke, DE Long, KL McMillan, DL Dill IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1994 | 859 | 1994 |
| Automatic verification of pipelined microprocessor control JR Burch, DL Dill Computer Aided Verification: 6th International Conference, CAV'94 Stanford …, 1994 | 829 | 1994 |
| Sequential circuit verification using symbolic model checking JR Burch, EM Clarke, KL McMillan, DL Dill Proceedings of the 27th ACM/IEEE Design Automation Conference, 46-51, 1991 | 726 | 1991 |
| Symbolic model checking with partitioned transition relations JR Burch, EM Clarke, DE Long Carnegie-Mellon University. Department of Computer Science, 1991 | 477 | 1991 |
| Representing circuits more efficiently in symbolic model checking JR Burch, EM Clarke, DE Long Proceedings of the 28th ACM/IEEE Design Automation Conference, 403-407, 1991 | 286 | 1991 |
| Techniques for verifying superscalar microprocessors JR Burch Proceedings of the 33rd annual Design Automation Conference, 552-557, 1996 | 167 | 1996 |
| Efficient validity checking for processor verification RB Jones, DL Dill, JR Burch Proceedings of IEEE International Conference on Computer Aided Design (ICCAD …, 1995 | 143 | 1995 |
| Automatic verification of sequential control systems using temporal logic I Moon, GJ Powers, JR Burch, EM Clarke AIChE Journal 38 (1), 67-75, 1992 | 135 | 1992 |
| Tight integration of combinational verification methods JR Burch, V Singhal Proceedings of the 1998 IEEE/ACM international conference on Computer-aided …, 1998 | 128 | 1998 |
| Using BDDs to verify multipliers JR Burch Proceedings of the 28th ACM/IEEE Design Automation Conference, 408-412, 1991 | 117 | 1991 |
| Efficient Boolean function matching Burch 1992 IEEE/ACM International Conference on Computer-Aided Design, 408-411, 1992 | 99 | 1992 |
| Safe BDD minimization using don't cares Y Hong, PA Beerel, JR Burch, KL McMillan Proceedings of the 34th annual Design Automation Conference, 208-213, 1997 | 91 | 1997 |
| Trace algebra for automatic verification of real-time concurrent systems. JR Burch | 90 | 1993 |
| Using simulation and satisfiability to compute flexibilities in Boolean networks A Mishchenko, JS Zhang, S Sinha, JR Burch, R Brayton, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006 | 80 | 2006 |
| Overcoming heterophobia: Modeling concurrency in heterogeneous systems J Burch, R Passerone, AL Sangiovanni-Vincentelli Proceedings Second International Conference on Application of Concurrency to …, 2001 | 58 | 2001 |
| Mechanically checking a lemma used in an automatic verification tool PJ Windley, JR Burch International Conference on Formal Methods in Computer-Aided Design, 362-376, 1996 | 52 | 1996 |
| Constraints specification at higher levels of abstraction F Balarin, J Burch, L Lavagno, Y Watanabe, R Passerone, ... Sixth IEEE International High-Level Design Validation and Test Workshop, 129-133, 2001 | 50 | 2001 |
| Robust latch mapping for combinational equivalence checking JR Burch, V Singhal Proceedings of the 1998 IEEE/ACM international conference on Computer-aided …, 1998 | 48 | 1998 |
| Integrating a boolean SAT solver into a router JR Burch, RF Damiano, PH Ho, JH Kukula US Patent 7,904,867, 2011 | 43 | 2011 |
