Implementation of templated DSA for via layer patterning at the 7nm node R Gronheid, J Doise, J Bekaert, BT Chan, I Karageorgos, J Ryckaert, ... Alternative Lithographic Technologies VII 9423, 13-22, 2015 | 34 | 2015 |
Hardware-Software Co-Design for Brain-Computer Interfaces I Karageorgos, K Sriram, J Veselý, M Wu, M Powell, D Borton, R Manohar, ... 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture …, 2020 | 23 | 2020 |
Design strategy for integrating DSA via patterning in sub-7 nm interconnects I Karageorgos, J Ryckaert, MC Tung, HSP Wong, R Gronheid, J Bekaert, ... Design-Process-Technology Co-optimization for Manufacturability X 9781, 201-209, 2016 | 19 | 2016 |
Impact of interconnect multiple-patterning variability on SRAMs I Karageorgos, M Stucchi, P Raghavan, J Ryckaert, Z Tokei, D Verkest, ... Proceedings of the 2015 Design, Automation & Test in Europe Conference …, 2015 | 11 | 2015 |
Design method and algorithms for directed self-assembly aware via layout decomposition in sub-7 nm circuits I Karageorgos, J Ryckaert, R Gronheid, MC Tung, HSP Wong, ... Journal of Micro/Nanolithography, MEMS, and MOEMS 15 (4), 043506-043506, 2016 | 10 | 2016 |
EUV patterned templates with grapho-epitaxy DSA at the N5/N7 logic nodes R Gronheid, C Boeckx, J Doise, J Bekaert, I Karageorgos, J Ryckaert, ... Extreme Ultraviolet (EUV) Lithography VII 9776, 97761W, 2016 | 10 | 2016 |
Chip-to-chip authentication method based on SRAM PUF and public key cryptography I Karageorgos, MM Isgenc, S Pagliarini, L Pileggi Journal of Hardware and Systems Security 3, 382-396, 2019 | 8 | 2019 |
Balancing Specialized Versus Flexible Computation in Brain–Computer Interfaces I Karageorgos, K Sriram, J Veselý, N Lindsay, X Wen, M Wu, M Powell, ... IEEE Micro 41 (3), 87-94, 2021 | 6 | 2021 |
Feasibility study of grapho-epitaxy DSA for complementing EUV lithography beyond N10 RG Chenxi Lin, Yi Zou, Davide Ambesi, Tamara Druzhinina, Sander Wuister ... International Symposium on DSA 2015, 2015 | 5* | 2015 |
HALO: A Hardware-Software Co-Designed Processor for Brain-Computer Interfaces I Karageorgos, K Sriram, X Wen, J Veselý, N Lindsay, M Wu, L Khazan, ... IEEE Micro, 2023 | 3 | 2023 |
Density driven placement of sub-DSA resolution assistant features (SDRAFs) D Guo, M Tung, I Karageorgos, HSP Wong, MDF Wong Design-Process-Technology Co-optimization for Manufacturability XI 10148 …, 2017 | 3 | 2017 |
Design strategy for layout of sub-resolution directed self-assembly assist features (sdrafs) CM Tung, J Doise, I Karageorgos, J Ryckaert, HSP Wong Proc. EIPBN 2016, 2016 | 2 | 2016 |
Impact of Interconnect Advanced Patterning Options on Circuit Design I Karageorgos | 1 | 2017 |
Opportunities and challenges for DSA in logic and memory R Gronheid, A Singh, J Doise, C Boeckx, I Karageorgos, J Ryckaert, ... Proc. SPIE 9777, Alternative Lithographic Technologies VIII, 2016 | 1 | 2016 |
Impact of DSA process variability on circuit performance I Karageorgos, J Doise, P Rincon Delgadillo, M Stucchi, R Baert, ... International Symposium on DSA 2016, 2016 | 1 | 2016 |
MODULAR, EXTENSIBLE COMPUTER PROCESSING ARCHITECTURE I Karageorgos, K Sriram, J Vesely, R Manohar, A Bhattacharjee US Patent App. 17/115,195, 2021 | | 2021 |
Balancing Specialized Versus Flexible Computation in Brain-Computer Interfaces K Sriram, I Karageorgos, N Lindsay, X Wen, R Manohar, A Bhattacharjee, ... | | 2021 |
Templated DSA with EUV-exposed pre-patterns C Boeckx, J Doise, I Karageorgos, J Ryckaert, BT Chan, R Gronheid, ... International Symposium on DSA 2016, 1-1, 2016 | | 2016 |
Density-Balancing Mask Assignment for Via Patterning with Directed Self-Assembly M Tung, D Guo, I Karageorgos, M Wong, HSP Wong International Symposium on DSA 2016, 2016 | | 2016 |
Design Method for the Integration of DSA Via Patterning in sub-7 nm Circuits I Karageorgos, MC Tung, HSP Wong, E Karageorgos, R Gronheid, ... Proc. INC12, 2016 | | 2016 |