| Voltage scheduling problem for dynamically variable voltage processors T Ishihara, H Yasuura Proceedings of the 1998 international symposium on Low power electronics and …, 1998 | 1068 | 1998 |
| Way-predicting set-associative cache for high performance and low energy consumption K Inoue, T Ishihara, K Murakami Proceedings of the 1999 international symposium on Low power electronics and …, 1999 | 445 | 1999 |
| Real-time task scheduling for a variable voltage processor T Okuma, T Ishihara, H Yasuura Proceedings 12th International Symposium on System Synthesis, 24-29, 1999 | 115 | 1999 |
| Estimating software power consumption T Ishihara, F Fallah US Patent 7,549,069, 2009 | 70 | 2009 |
| Wide-supply-range all-digital leakage variation sensor for on-chip process and temperature monitoring AKMM Islam, J Shiomi, T Ishihara, H Onodera IEEE Journal of Solid-State Circuits 50 (11), 2475-2490, 2015 | 60 | 2015 |
| A power reduction technique with object code merging for application specific embedded processors T Ishihara, H Yasuura Proceedings of the conference on design, automation and test in Europe, 617-623, 2000 | 60 | 2000 |
| Software energy reduction techniques for variable-voltage processors T Okuma, H Yasuura, T Ishihara IEEE Design & Test of Computers 18 (2), 31-41, 2001 | 53 | 2001 |
| Instruction scheduling for power reduction in processor-based system design H Tomiyama, T Ishihara, A Inoue, H Yasuura Proceedings Design, Automation and Test in Europe, 855-860, 1998 | 47 | 1998 |
| An RTOS in hardware for energy efficient software-based TCP/IP processing N Maruyama, T Ishihara, H Yasuura 2010 IEEE 8th symposium on application specific processors (SASP), 58-63, 2010 | 44 | 2010 |
| A system level memory power optimization technique using multiple supply and threshold voltages T Ishihara, K Asada Proceedings of the 2001 Asia and South Pacific Design Automation Conference …, 2001 | 40 | 2001 |
| A non-uniform cache architecture for low power system design T Ishihara, F Fallah Proceedings of the 2005 international symposium on Low power electronics and …, 2005 | 33 | 2005 |
| Minimum energy point tracking using combined dynamic voltage scaling and adaptive body biasing S Hokimoto, T Ishihara, H Onodera 2016 29th IEEE International System-on-Chip Conference (SOCC), 1-6, 2016 | 31 | 2016 |
| SRAM leakage reduction by row/column redundancy under random within-die delay variation M Goudarzi, T Ishihara IEEE transactions on very large scale integration (VLSI) systems 18 (12 …, 2009 | 31 | 2009 |
| A simulation-based soft error estimation methodology for computer systems M Sugihara, T Ishihara, K Hashimoto, M Muroyama 7th International Symposium on Quality Electronic Design (ISQED'06), 8 pp.-203, 2006 | 29 | 2006 |
| A high-performance and low-power cache architecture with speculative way-selection K Inoue, T Ishihara, K Murakami IEICE transactions on electronics 83 (2), 186-194, 2000 | 29 | 2000 |
| Analysis and comparison of XOR cell structures for low voltage circuit design S Nishizawa, T Ishihara, H Onodera International Symposium on Quality Electronic Design (ISQED), 703-708, 2013 | 28 | 2013 |
| AMPLE: An adaptive multi-performance processor for low-energy embedded applications T Ishihara, S Yamaguchi, Y Ishitobi, T Matsumura, Y Kunitake, Y Oyama, ... 2008 Symposium on Application Specific Processors, 83-88, 2008 | 28 | 2008 |
| Code and data placement for embedded processors with scratchpad and cache memories Y Ishitobi, T Ishihara, H Yasuura Journal of Signal Processing Systems 60, 211-224, 2010 | 26 | 2010 |
| A way memoization technique for reducing power consumption of caches in application specific integrated processors T Ishihara, F Fallah Design, Automation and Test in Europe, 358-363, 2005 | 26 | 2005 |
| Minimizing inter-task interferences in scratch-pad memory usage for reducing the energy consumption of multi-task systems L Gauthier, T Ishihara, H Takase, H Tomiyama, H Takada Proceedings of the 2010 international conference on Compilers, architectures …, 2010 | 25 | 2010 |
