Ewan Towie
Ewan Towie
Synopsys ltd.
Verified email at synopsys.com - Homepage
Title
Cited by
Cited by
Year
Impact of precisely positioned dopants on the performance of an ultimate silicon nanowire transistor: A full three-dimensional NEGF simulation study
VP Georgiev, EA Towie, A Asenov
IEEE Transactions on Electron Devices 60 (3), 965-971, 2013
282013
Simulation study of the impact of quantum confinement on the electrostatically driven performance of n-type nanowire transistors
Y Wang, T Al-Ameri, X Wang, VP Georgiev, E Towie, SM Amoroso, ...
IEEE Transactions on Electron Devices 62 (10), 3229-3236, 2015
192015
Design and analysis of the In0. 53Ga0. 47As implant-free quantum-well device structure
B Benbakhti, K Kalna, KH Chan, E Towie, G Hellings, G Eneman, ...
Microelectronic engineering 88 (4), 358-361, 2011
122011
Impact of strain on the performance of Si nanowires transistors at the scaling limit: A 3D Monte Carlo/2D Poisson Schrodinger simulation study
T Al-Ameri, VP Georgiev, FA Lema, T Sadi, X Wang, E Towie, C Riddet, ...
2016 International Conference on Simulation of Semiconductor Processes and …, 2016
112016
Experimental and simulation study of silicon nanowire transistors using heavily doped channels
VP Georgiev, MM Mirza, AI Dochioiu, F Adamu-Lema, SM Amoroso, ...
IEEE Transactions on Nanotechnology 16 (5), 727-735, 2017
102017
Inverse Scaling Trends for Charge-Trapping-Induced Degradation of FinFETs Performance
SM Amoroso, VP Georgiev, L Gerrer, E Towie, X Wang, C Riddet, ...
Electron Devices, IEEE Transactions on 61 (12), 4014-4018, 2014
102014
3d multi-subband ensemble Monte Carlo simulator of FinFETs and nanowire transistors
C Sampedro, L Donetti, F Gamiz, A Godoy, FJ Garcia-Ruiz, VP Georgiev, ...
2014 International Conference on Simulation of Semiconductor Processes and …, 2014
102014
Impact of quantum confinement on transport and the electrostatic driven performance of silicon nanowire transistors at the scaling limit
T Al-Ameri, VP Georgiev, T Sadi, Y Wang, F Adamu-Lema, X Wang, ...
Solid-State Electronics 129, 73-80, 2017
92017
Predicting future technology performance
A Asenov, C Alexander, C Riddet, E Towie
Proceedings of the 50th Annual Design Automation Conference, 1-6, 2013
72013
Variability-aware TCAD based design-technology co-optimization platform for 7nm node nanowire and beyond
Y Wang, B Cheng, X Wang, E Towie, C Riddet, AR Brown, SM Amoroso, ...
2016 IEEE Symposium on VLSI Technology, 1-2, 2016
62016
One-dimensional multi-subband Monte Carlo simulation of charge transport in Si nanowire transistors
T Sadi, E Towie, M Nedjalkov, C Riddet, C Alexander, L Wang, ...
2016 International Conference on Simulation of Semiconductor Processes and …, 2016
42016
Numerical analysis of the new implant-free quantum-well CMOS: DualLogic approach
B Benbakhti, KH Chan, E Towie, K Kalna, C Riddet, X Wang, G Eneman, ...
Solid-state electronics 63 (1), 14-18, 2011
42011
Monte Carlo analysis of In0.53Ga0.47as Implant-Free Quantum-Well device performance
B Benbakhti, E Towie, K Kalna, G Hellings, G Eneman, K De Meyer, ...
2010 Silicon Nanoelectronics Workshop, 1-2, 2010
42010
Performance of vertically stacked horizontal Si nanowires transistors: A 3D Monte Carlo/2D Poisson Schrodinger simulation study
T Al-Ameri, VP Georgiev, FA Lema, T Sadi, E Towie, C Riddet, ...
2016 IEEE Nanotechnology Materials and Devices Conference (NMDC), 1-2, 2016
32016
Impact of the statistical variability on 15nm III–V and Ge MOSFET based SRAM design
SY Liao, EA Towie, D Balaz, C Riddet, B Cheng, A Asenov
2013 14th International Conference on Ultimate Integration on Silicon (ULIS …, 2013
32013
Remotely screened electron-impurity scattering model for nanoscale MOSFETs
EA Towie, JR Watling, JR Barker
Semiconductor science and technology 26 (5), 055008, 2011
32011
Influence of quantum confinement effects over device performance in circular and elliptical silicon nanowire transistors
VP Georgiev, T Ali, Y Wang, L Gerrer, SM Amoroso, A Asenov
2015 International Workshop on Computational Electronics (IWCE), 1-4, 2015
22015
Interactions Between Precisely Placed Dopants and Interface Roughness in Silicon Nanowire Transistors: Full 3-D NEGF Simulation Study
VP Georgiev, EA Towie, A Asenov
Simulation of Semiconductor Processes and Devices (SISPAD), 2013 …, 2013
22013
3D Monte Carlo Simulation of III-V Implant-Free Quantum-Well and FinFET MOSFETs
EA Towie, C Riddet, A Asenov
16th International Workshop on Computational Electronics, 2013, 2013
22013
Experimental and simulation study of a high current 1D silicon nanowire transistor using heavily doped channels
VP Georgiev, MM Mirza, AI Dochioiu, FA Lema, SM Amoroso, E Towie, ...
2016 IEEE Nanotechnology Materials and Devices Conference (NMDC), 1-3, 2016
12016
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