Ibrahim Hur
Title
Cited by
Cited by
Year
An evaluation of high-level mechanistic core models
TE Carlson, W Heirman, S Eyerman, I Hur, L Eeckhout
ACM Transactions on Architecture and Code Optimization (TACO) 11 (3), 1-25, 2014
2212014
A comprehensive approach to DRAM power management
I Hur, C Lin
2008 IEEE 14th International Symposium on High Performance Computer …, 2008
1672008
Adaptive history-based memory schedulers
I Hur, C Lin
37th International Symposium on Microarchitecture (MICRO-37'04), 343-354, 2004
1662004
Memory prefetching using adaptive stream detection
I Hur, C Lin
Microarchitecture, 2006. MICRO-39. 39th Annual IEEE/ACM International …, 2006
1252006
Power-aware multi-core simulation for early design stage hardware/software co-optimization
W Heirman, S Sarkar, TE Carlson, I Hur, L Eeckhout
Proceedings of the 21st international conference on Parallel architectures …, 2012
472012
DRAM power management in a memory controller
I Hur, C Lin
US Patent 7,739,461, 2010
442010
Discovering and understanding performance bottlenecks in transactional applications
F Zyulkyarov, S Stipic, T Harris, OS Unsal, A Cristal, I Hur, M Valero
2010 19th International Conference on Parallel Architectures and Compilation …, 2010
402010
RMS-TM: A comprehensive benchmark suite for transactional memory systems
G Kestor, V Karakostas, OS Unsal, A Cristal, I Hur, M Valero
Proceeding of the second joint WOSP/SIPEW international conference on …, 2011
352011
Memory scheduling for modern microprocessors
I Hur, C Lin
ACM Transactions on Computer Systems (TOCS) 25 (4), 10-es, 2007
332007
Undersubscribed threading on clustered cache architectures
W Heirman, TE Carlson, K Van Craeynest, I Hur, A Jaleel, L Eeckhout
2014 IEEE 20th International Symposium on High Performance Computer …, 2014
292014
FaulTM: Fault-tolerance using hardware transactional memory
G Yalcin, O Unsal, I Hur, A Cristal, M Valero
292010
Probabilistic method for performing memory prefetching
I Hur, C Lin
US Patent 7,856,533, 2010
272010
Cooler for an electronic device
E Lopatinsky, D Schaefer, S Rosenfeld, L Fedoseyev
US Patent 6,698,505, 2004
272004
Memory controller with programmable regression model for power control
I Hur, C Lin
US Patent 7,724,602, 2010
262010
The velox transactional memory stack
Y Afek, U Drepper, P Felber, C Fetzer, V Gramoli, M Hohmuth, E Riviere, ...
IEEE micro 30 (5), 76-87, 2010
252010
Feedback mechanisms for improving probabilistic memory prefetching
I Hur, C Lin
2009 IEEE 15th International Symposium on High Performance Computer …, 2009
242009
Exploring optimizations on shared-memory platforms for parallel triangle counting algorithms
AS Tom, N Sundaram, NK Ahmed, S Smith, S Eyerman, M Kodiyath, I Hur, ...
2017 IEEE High Performance Extreme Computing Conference (HPEC), 1-7, 2017
212017
STM2: A Parallel STM for High Performance Simultaneous Multithreading Systems
G Kestor, R Gioiosa, T Harris, OS Unsal, A Cristal, I Hur, M Valero
Parallel Architectures and Compilation Techniques (PACT), 2011 International …, 2011
212011
Using a reconfigurable l1 data cache for efficient version management in hardware transactional memory
A Armejach, A Seyedi, R Titos-Gil, I Hur, A Cristal, OS Unsal, M Valero
Parallel Architectures and Compilation Techniques (PACT), 2011 International …, 2011
192011
Automatic SMT threading for OpenMP applications on the Intel Xeon Phi co-processor
W Heirman, TE Carlson, K Van Craeynest, I Hur, A Jaleel, L Eeckhout
Proceedings of the 4th International Workshop on Runtime and Operating …, 2014
142014
The system can't perform the operation now. Try again later.
Articles 1–20