Vladimir Stojanovic
Vladimir Stojanovic
Associate Professor of Electrical Engineering and Computer Sciences, University of California
Verifierad e-postadress på berkeley.edu - Startsida
TitelCiteras avÅr
Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems
V Stojanovic, VG Oklobdzija
IEEE Journal of solid-state circuits 34 (4), 536-548, 1999
Single-chip microprocessor that communicates directly using light
C Sun, MT Wade, Y Lee, JS Orcutt, L Alloatti, MS Georgas, AS Waterman, ...
Nature 528 (7583), 534, 2015
Building manycore processor to DRAM networks with monolithic silicon photonics
C Batten, A Joshi, J Orcutt, A Khilo, B Moss, C Holzwarth, M Popović, H Li, ...
IEEE Symposium on High-Performance Interconnects, 21-30, 2008
Improved sense-amplifier-based flip-flop: Design and measurements
B Nikolic, VG Oklobdzija, V Stojanovic, W Jia, JKS Chiu, MMT Leung
IEEE Journal of Solid-State Circuits 35 (6), 876-884, 2000
DSENT-a tool connecting emerging photonics with electronics for opto-electronic networks-on-chip modeling
C Sun, CHO Chen, G Kurian, L Wei, J Miller, A Agarwal, LS Peh, ...
2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip, 201-210, 2012
Silicon-photonic clos networks for global on-chip communication
A Joshi, C Batten, YJ Kwon, S Beamer, I Shamim, K Asanovic, ...
2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, 124-133, 2009
Design and analysis of a hardware-efficient compressed sensing architecture for data compression in wireless sensors
F Chen, AP Chandrakasan, VM Stojanovic
IEEE Journal of Solid-State Circuits 47 (3), 744-756, 2012
Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell
JL Zerbe, CW Werner, V Stojanovic, F Chen, J Wei, G Tsang, D Kim, ...
IEEE Journal of Solid-State Circuits 38 (12), 2121-2130, 2003
Modeling and analysis of high-speed links
V Stojanovic, M Horowitz
Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003 …, 2003
Methods for true energy-performance optimization
D Markovic, V Stojanovic, B Nikolic, MA Horowitz, RW Brodersen
IEEE Journal of Solid-State Circuits 39 (8), 1282-1293, 2004
Open foundry platform for high-performance electronic-photonic integration
JS Orcutt, B Moss, C Sun, J Leu, M Georgas, J Shainline, E Zgraggen, ...
Optics Express 20 (11), 12222-12232, 2012
Digital system clocking: high-performance and low-power aspects
VG Oklobdzija, VM Stojanovic, DM Markovic, NM Nedovic
John Wiley & Sons, 2005
Circuits and techniques for high-resolution measurement of on-chip power supply noise
E Alon, V Stojanovic, MA Horowitz
Solid-State Circuits, IEEE Journal of 40 (4), 820-828, 2005
Demonstration of integrated micro-electro-mechanical relay circuits for VLSI applications
M Spencer, F Chen, CC Wang, R Nathanael, H Fariborzi, A Gupta, H Kam, ...
IEEE Journal of Solid-State Circuits 46 (1), 308-320, 2010
Silicon photonics for compact, energy-efficient interconnects
T Barwicz, H Byun, F Gan, CW Holzwarth, MA Popovic, PT Rakich, ...
Journal of Optical Networking 6 (1), 63-73, 2007
Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery
V Stojanovic, A Ho, BW Garlepp, F Chen, J Wei, G Tsang, E Alon, ...
IEEE Journal of Solid-State Circuits 40 (4), 1012-1026, 2005
Integrated circuit design with NEM relays
F Chen, H Kam, D Markovic, TJK Liu, V Stojanovic, E Alon
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided …, 2008
Nanophotonic integration in state-of-the-art CMOS foundries
JS Orcutt, A Khilo, CW Holzwarth, MA Popović, H Li, J Sun, T Bonifield, ...
Optics express 19 (3), 2335-2346, 2011
Methods for true power minimization
RW Brodersen, MA Horowitz, D Markovic, B Nikolic, V Stojanovic
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided …, 2002
Addressing link-level design tradeoffs for integrated photonic interconnects
M Georgas, J Leu, B Moss, C Sun, V Stojanović
2011 IEEE Custom Integrated Circuits Conference (CICC), 1-8, 2011
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Artiklar 1–20