| 29.2 A transmitter and receiver for 100Gb/s coherent networks with integrated 4× 64GS/s 8b ADCs and DACs in 20nm CMOS J Cao, D Cui, A Nazemi, T He, G Li, B Catli, M Khanpour, K Hu, T Ali, ... 2017 IEEE International Solid-State Circuits Conference (ISSCC), 484-485, 2017 | 83 | 2017 |
| 6.2 A 460mW 112Gb/s DSP-based transceiver with 38dB loss compensation for next-generation data centers in 7nm FinFET technology T Ali, E Chen, H Park, R Yousry, YM Ying, M Abdullatif, M Gandara, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 118-120, 2020 | 75 | 2020 |
| A 4.6 GHz MDLL with− 46dBc reference spur and aperture position tuning TA Ali, AA Hafez, R Drost, R Ho, CKK Yang 2011 IEEE International Solid-State Circuits Conference, 466-468, 2011 | 53 | 2011 |
| 6.4 A 180mW 56Gb/s DSP-based transceiver for high density IOs in data center switches in 7nm FinFET technology T Ali, R Yousry, H Park, E Chen, PS Weng, YC Huang, CC Liu, CH Wu, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 118-120, 2019 | 46 | 2019 |
| A 3.8 mW/Gbps quad-channel 8.5–13 Gbps serial link with a 5 tap DFE and a 4 tap transmit FFE in 28 nm CMOS N Kocaman, T Ali, LP Rao, U Singh, M Abdul-Latif, Y Liu, AA Hafez, ... IEEE Journal of Solid-State Circuits 51 (4), 881-892, 2016 | 38 | 2016 |
| 11.1 a 1.7 pJ/b 112Gb/s XSR transceiver for intra-package communication in 7nm FinFET technology R Yousry, E Chen, YM Ying, M Abdullatif, M Elbadry, A ElShater, TB Liu, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 180-182, 2021 | 34 | 2021 |
| A sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications B Çatlı, A Nazemi, T Ali, S Fallahi, Y Liu, J Kim, M Abdul-Latif, MR Ahmadi, ... Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 1-4, 2013 | 31 | 2013 |
| A 12-mW Fully Integrated Low-IF dual-band GPS Receiver on 0.13-μm CMOS TA Abdelrahim, T Elesseily, AS Abdou, KMW Sharaf 2007 IEEE International Symposium on Circuits and Systems, 3034-3038, 2007 | 29 | 2007 |
| A dual-channel 23-Gbps CMOS transmitter/receiver chipset for 40-Gbps RZ-DQPSK and CS-RZ-DQPSK optical transmission D Cui, B Raghavan, U Singh, A Vasani, Z Huang, D Pi, M Khanpour, ... IEEE journal of solid-state circuits 47 (12), 3249-3260, 2012 | 28 | 2012 |
| Aperture generating circuit for a multiplying delay-locked loop TM Ali, RJ Drost, CKK Yang US Patent 7,994,832, 2011 | 19 | 2011 |
| A concurrent dual-band mixer for 900-MHz/1.8 GHz RF front-ends TA Abdelrheem, HY Elhak, KM Sharaf 2003 46th Midwest Symposium on Circuits and Systems 3, 1291-1294, 2003 | 16 | 2003 |
| Transmission line driver with output swing control ALI Tamer US Patent 8,994,399, 2015 | 13 | 2015 |
| A 2.8 mW/Gb/s quad-channel 8.5–11.4 Gb/s quasi-digital transceiver in 28 nm CMOS A Nazemi, H Maarefi, B Çatlı, MR Ahmadi, S Fallahi, T Ali, M Abdul-Latif, ... 2013 Symposium on VLSI Circuits, C276-C277, 2013 | 13 | 2013 |
| 10Gb/s serial I/O receiver based on variable reference ADC EH Chen, R Yousry, T Ali, CKK Yang 2011 Symposium on VLSI Circuits-Digest of Technical Papers, 288-289, 2011 | 12 | 2011 |
| Compact low-power fully digital CMOS clock generation apparatus for high-speed SerDes MR Ahmadi, S Fallahi, ALI Tamer, A Nazemi, H Maarefi, B Catli, A Momtaz US Patent 9,001,869, 2015 | 11 | 2015 |
| A 4.63 pJ/b 112Gb/s DSP-Based PAM-4 Transceiver for a Large-Scale Switch in 5nm FinFET H Park, M Abdullatif, E Chen, A Elmallah, Q Nehal, M Gandara, TB Liu, ... 2023 IEEE International Solid-State Circuits Conference (ISSCC), 5-7, 2023 | 10 | 2023 |
| A 3.8 mW/Gbps quad-channel 8.5–13 Gbps serial link with a 5-tap DFE and a 4-tap transmit FFE in 28 nm CMOS T Ali, L Rao, U Singh, M Abdul-Latif, Y Liu, AA Hafez, H Park, A Vasani, ... 2015 Symposium on VLSI Circuits (VLSI Circuits), C348-C349, 2015 | 9 | 2015 |
| A dual 23Gb/s CMOS transmitter/receiver chipset for 40Gb/s RZ-DQPSK and CS-RZ-DQPSK optical transmission D Cui, B Raghavan, U Singh, A Vasani, Z Huang, D Pi, M Khanpour, ... 2012 IEEE International Solid-State Circuits Conference, 330-332, 2012 | 9 | 2012 |
| Time-interleaved high-speed digital-to-analog converter (DAC) architecture with spur calibration A Garg, A Nazemi, AJ Vasani, HG Rhew, J Zhang, J Cao, MH Nazari, ... US Patent 9,685,969, 2017 | 8 | 2017 |
| High bandwidth equalizer and limiting amplifier ALI Tamer, A Nazemi, N Kocaman US Patent 9,136,904, 2015 | 8 | 2015 |
Namik KocamanBroadcom CorporationVerified email at broadcom.com
