| kNN-STUFF: kNN STreaming unit for FPGAs J Vieira, RP Duarte, HC Neto IEEE Access 7, 170864-170877, 2019 | 32 | 2019 |
| A product engine for energy-efficient execution of binary neural networks using resistive memories J Vieira, E Giacomin, Y Qureshi, M Zapater, X Tang, S Kvatinsky, ... 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration …, 2019 | 11 | 2019 |
| Exploiting compute caches for memory bound vector operations J Vieira, N Roma, P Tomás, P Ienne, G Falcao 2018 30th International Symposium on Computer Architecture and High …, 2018 | 9 | 2018 |
| Processing convolutional neural networks on cache J Vieira, N Roma, G Falcao, P Tomás ICASSP 2020-2020 IEEE international conference on acoustics, speech and …, 2020 | 4 | 2020 |
| gem5-ndp: Near-Data Processing Architecture Simulation From Low Level Caches to DRAM J Vieira, N Roma, G Falcao, P Tomás 2022 IEEE 34th International Symposium on Computer Architecture and High …, 2022 | 3 | 2022 |
| A compute cache system for signal processing applications J Vieira, N Roma, G Falcao, P Tomás Journal of Signal Processing Systems, 1-14, 2021 | 3 | 2021 |
| Accelerating inference on binary neural networks with digital RRAM processing J Vieira, E Giacomin, Y Qureshi, M Zapater, X Tang, S Kvatinsky, ... VLSI-SoC: New Technology Enabler: 27th IFIP WG 10.5/IEEE International …, 2020 | 2 | 2020 |
| gem5-accel: A Pre-RTL Simulation Toolchain for Accelerator Architecture Validation J Vieira, N Roma, G Falcao, P Tomás IEEE Computer Architecture Letters, 2023 | 1 | 2023 |
| NDPmulator: Enabling Full-System Simulation for Near-Data Accelerators from Caches to DRAM J Vieira, N Roma, G Falcao, P Tomás IEEE Access, 2024 | | 2024 |
| Assessing On-Chip High-Performance Interfaces on Xilinx and Intel FPGA-SoC Devices Reconfigurable Computing 2019/2020 J Vieira | | 2023 |
| Digital RRAM-based convolutional block P Gaillardon, E Giacomin, J Vieira US Patent 11,450,385, 2022 | | 2022 |
| Exploiting Processing Near Cache for Memory Bound Vector Operations JMMP Vieira | | 2018 |
| Playing BlokusDuo in a ZYNQ Device: A Quest for an Efficient Algorithm J Vieira | | |
| Exploiting Near-Cache Processing for Memory Bound Vector Operations J Vieira | | |
| Tying Clustering and Neural Networks for more general Memory-Augmented Neural Networks J Vieira, M Barzegar, SM Cherati | | |
