David Brooks
David Brooks
Haley Family Professor of Computer Science, Harvard University
Verified email at eecs.harvard.edu
TitleCited byYear
Wattch: A framework for architectural-level power analysis and optimizations
D Brooks, V Tiwari, M Martonosi
ACM SIGARCH Computer Architecture News 28 (2), 83-94, 2000
Dynamic thermal management for high-performance microprocessors
D Brooks, M Martonosi
Proceedings HPCA Seventh International Symposium on High-Performance …, 2001
System level analysis of fast, per-core DVFS using on-chip switching regulators
W Kim, MS Gupta, GY Wei, D Brooks
2008 IEEE 14th International Symposium on High Performance Computer …, 2008
Power-aware microarchitecture: Design and modeling challenges for next-generation microprocessors
DM Brooks, P Bose, SE Schuster, H Jacobson, PN Kudva, ...
IEEE Micro 20 (6), 26-44, 2000
Accurate and efficient regression modeling for microarchitectural performance and power prediction
BC Lee, DM Brooks
ACM SIGOPS Operating Systems Review 40 (5), 185-194, 2006
Dynamically exploiting narrow width operands to improve processor power and performance
D Brooks, M Martonosi
Proceedings Fifth International Symposium on High-Performance Computer …, 1999
Thread motion: fine-grained power management for multi-core systems
KK Rangan, GY Wei, D Brooks
ACM SIGARCH Computer Architecture News 37 (3), 302-313, 2009
Minerva: Enabling low-power, highly-accurate deep neural network accelerators
B Reagen, P Whatmough, R Adolf, S Rama, H Lee, SK Lee, ...
2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture …, 2016
A dynamic compilation framework for controlling microprocessor energy and performance
Q Wu, VJ Reddi, Y Wu, J Lee, D Connors, D Brooks, M Martonosi, ...
38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'05 …, 2005
Understanding voltage variations in chip multiprocessors using a distributed power-delivery network
MS Gupta, JL Oatley, R Joseph, GY Wei, DM Brooks
2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007
Profiling a warehouse-scale computer
S Kanev, JP Darago, K Hazelwood, P Ranganathan, T Moseley, GY Wei, ...
Proceedings of the 42nd Annual International Symposium on Computer …, 2015
An ultra low power system architecture for sensor network applications
M Hempstead, N Tripathi, P Mauro, GY Wei, D Brooks
32nd International Symposium on Computer Architecture (ISCA'05), 208-219, 2005
A fully-integrated 3-level DC-DC converter for nanosecond-scale DVFS
W Kim, D Brooks, GY Wei
IEEE Journal of Solid-State Circuits 47 (1), 206-219, 2011
Methods of inference and learning for performance modeling of parallel applications
BC Lee, DM Brooks, BR de Supinski, M Schulz, K Singh, SA McKee
Proceedings of the 12th ACM SIGPLAN symposium on Principles and practice of …, 2007
Performance, energy, and thermal considerations for SMT and CMP architectures
Y Li, K Skadron, D Brooks, Z Hu
11th International Symposium on High-Performance Computer Architecture, 71-82, 2005
Aladdin: A pre-rtl, power-performance accelerator simulator enabling large design space exploration of customized architectures
YS Shao, B Reagen, GY Wei, D Brooks
2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA …, 2014
CMP design space exploration subject to physical constraints
Y Li, B Lee, D Brooks, Z Hu, K Skadron
The Twelfth International Symposium on High-Performance Computer …, 2006
Control techniques to eliminate voltage emergencies in high performance processors
R Joseph, D Brooks, M Martonosi
The Ninth International Symposium on High-Performance Computer Architecture …, 2003
Optimizing pipelines for power and performance
V Srinivasan, D Brooks, M Gschwind, P Bose, V Zyuban, PN Strenski, ...
35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002 …, 2002
Mitigating the impact of process variations on processor register files and execution units
X Liang, D Brooks
2006 39th Annual IEEE/ACM International Symposium on Microarchitecture …, 2006
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