| Intel threading building blocks: outfitting C++ for multi-core processor parallelism J Reinders " O'Reilly Media, Inc.", 2007 | 2011 | 2007 |
| Intel threading building blocks: outfitting C++ for multi-core processor parallelism J Reinders " O'Reilly Media, Inc.", 2007 | 2003 | 2007 |
| Structured parallel programming: patterns for efficient computation M McCool, J Reinders, A Robison Elsevier, 2012 | 780 | 2012 |
| Intel Xeon Phi coprocessor high performance programming J Jeffers, J Reinders Newnes, 2013 | 776 | 2013 |
| Intel Xeon Phi processor high performance programming: knights landing edition J Jeffers, J Reinders, A Sodani Morgan Kaufmann, 2016 | 414 | 2016 |
| VTune performance analyzer essentials J Reinders Intel Press, 2005 | 234 | 2005 |
| VTune performance analyzer essentials J Reinders Intel Press, 2005 | 234 | 2005 |
| High performance parallelism pearls volume two: multicore and many-core programming approaches J Jeffers, J Reinders Morgan Kaufmann, 2015 | 145 | 2015 |
| High performance parallelism pearls volume two: multicore and many-core programming approaches J Jeffers, J Reinders Morgan Kaufmann, 2015 | 145 | 2015 |
| Data parallel C++: mastering DPC++ for programming of heterogeneous systems using C++ and SYCL J Reinders, B Ashbaugh, J Brodman, M Kinsner, J Pennycook, X Tian Springer Nature, 2021 | 106 | 2021 |
| An overview of programming for Intel Xeon processors and Intel Xeon Phi coprocessors J Reinders Intel Corporation, Santa Clara 1, 1550002, 2012 | 94 | 2012 |
| Pro TBB: C++ parallel programming with threading building blocks M Voss, R Asenjo, J Reinders Apress, 2019 | 80 | 2019 |
| Method and apparatus for scheduling instructions for execution on a multi-issue architecture computer JR Reinders US Patent 5,819,088, 1998 | 75 | 1998 |
| Intel AVX-512 instructions J Reinders Intel Software Developer Zone, 2017 | 64 | 2017 |
| Transactional synchronization in Haswell J Reinders Intel Software Network, 2012 | 60 | 2012 |
| Characterization and optimization methodology applied to stencil computations C Andreolli, P Thierry, L Borges, G Skinner, C Yount, J Jeffers, J Reinders High Performance Parallelism Pearls, 377-396, 2015 | 44 | 2015 |
| Method for managing free physical pages that reduces trashing to improve system performance J Reinders, J Bonasera US Patent 5,897,660, 1999 | 37 | 1999 |
| Display of translations in an interleaved fashion with variable spacing J Reinders US Patent App. 09/962,721, 2003 | 33 | 2003 |
| Method for generating and transferring redundancy bits between levels of a cache memory hierarchy J Reinders US Patent 6,044,437, 2000 | 26 | 2000 |
| Data Parallel C+ J Reinders Springer Nature, 2021 | 13 | 2021 |
James JeffersNVIDIA CorporationVerified email at intel.com
