| Improved volume diagnosis throughput using dynamic design partitioning X Fan, H Tang, Y Huang, WT Cheng, SM Reddy, B Benware 2012 IEEE International Test Conference, 1-10, 2012 | 41 | 2012 |
| An on-chip test clock control scheme for multi-clock at-speed testing FAN Xiao-Xin, HU Yu, W Laung-Terng 16th Asian Test Symposium (ATS 2007), 341-348, 2007 | 31 | 2007 |
| Localized random access scan: Towards low area and routing overhead Y Hu, X Fu, X Fan, H Fujiwara 2008 Asia and South Pacific Design Automation Conference, 565-570, 2008 | 30 | 2008 |
| Diagnosis of cell internal defects with multi-cycle test patterns X Fan, M Sharma, WT Cheng, SM Reddy 2012 IEEE 21st Asian Test Symposium, 7-12, 2012 | 19 | 2012 |
| Distributed Dynamic Partitioning Based Diagnosis of Scan Chain Y Huang, X Fan, H Tang, M Sharma, WT Cheng, B Benware, SM Reddy VLSI Test Symposium, 2013 | 16 | 2013 |
| The design-for-testability features of a general purpose microprocessor D Wang, X Fan, X Fu, H Liu, K Wen, R Li, H Li, Y Hu, X Li 2007 IEEE International Test Conference, 1-9, 2007 | 14 | 2007 |
| Dynamic design partitioning for diagnosis H Tang, Y Huang, WT Cheng, RB Benware, X Fan US Patent 9,336,107, 2016 | 10 | 2016 |
| Fault diagnosis based on design partitioning H Tang, WTJ Cheng, RB Benware, X Fan US Patent 8,707,232, 2014 | 9 | 2014 |
| Genetic algorithm based approach for segmented testing X Fan, SM Reddy, S Wang, S Kajihara, Y Sato 2011 IEEE/IFIP 41st International Conference on Dependable Systems and …, 2011 | 9 | 2011 |
| On using design partitioning to reduce diagnosis memory footprint X Fan, H Tang, SM Reddy, WT Cheng, B Benware 2011 Asian Test Symposium, 219-225, 2011 | 8 | 2011 |
| Max-fill: A method to generate high quality delay tests X Fan, SM Reddy, I Pomeranz 14th IEEE International Symposium on Design and Diagnostics of Electronic …, 2011 | 8 | 2011 |
| A Pattern Partitioning Algorithm for Field Test S Wang, S Kajihara, Y Sato, X Fan, S Reddy IEEE 2nd International Workshop on Reliability Aware System Design and Test …, 2011 | 8 | 2011 |
| An at-speed Scan Test Scheme Using On-Chip PLL 范小鑫， 李华伟， 胡瑜， 李晓维 Journal of Computer-Aided Design & Computer Graphics 19 (3), 366-370, 2007 | 5* | 2007 |
| Dynamic design partitioning for scan chain diagnosis Y Huang, H Tang, WT Cheng, RB Benware, M Sharma, X Fan US Patent 9,244,125, 2016 | 4 | 2016 |
| Fault diagnosis of VLSI designs: cell internal faults and volume diagnosis throughput X Fan University of Iowa, 2012 | 1 | 2012 |
| FINDING DEEP RTL BUGS THROUGH FORMAL VERIFICATION X Feng, X Fan, C Campos, L Li, M Pedneau VLSI Test Symposium (VTS), 2017 IEEE 35th, 2017 | | 2017 |
| Max-Fill: A Method to Generate High Quality Partially-functional Broadside Delay Tests X Fan, SM Reddy, I Pomeranz The IEEE 19th North Atlantic Test Workshop, pp 2.1, 2010 | | 2010 |
