| Time-Multiplexed 1687-Network for Test Cost Reduction MA Ansari, J Jung, D Kim, S Park IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017 | 14 | 2017 |
| Test Architecture for Systolic Array of Edge-Based AI Accelerator US Solangi, M Ibtesam, MA Ansari, J Kim, S Park IEEE Access 9, 96700-96710, 2021 | 13 | 2021 |
| Highly efficient test architecture for low power AI accelerators M Ibtesam, US Solangi, J Kim, MA Ansari, S Park IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2021 | 12 | 2021 |
| SONAR based obstacle detection and avoidance algorithm MA Ansari, FA Umrani Signal Acquisition and Processing, 2009. ICSAP 2009. International …, 2009 | 11 | 2009 |
| Parallel test method for NoC-based SoCs MA Ansari, J Song, M Kim, S Park SoC Design Conference (ISOCC), 2009 International, 116-119, 2009 | 8 | 2009 |
| On Diagnosing the Aging Level of Automotive Semiconductor Devices J Jung, MA Ansari, D Kim, H Yi, S Park IEEE Transactions on Circuits and Systems II: Express Briefs 64 (7), 822-826, 2017 | 7 | 2017 |
| Time-multiplexed test access architecture for stacked integrated circuits MA Ansari, J Jung, D Kim, S Park IEICE Electronics Express 13 (14), 20160314-20160314, 2016 | 7 | 2016 |
| Hybrid test data transportation scheme for advanced NoC-based SoCs MA Ansari, D Kim, J Jung, S Park JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 15 (1), 85-95, 2015 | 7 | 2015 |
| Scan-Puf: Puf Elements Selection Methods for Viable IC Identification D Kim, MA Ansari, J Jung, S Park Test Symposium (ATS), 2015 IEEE 24th Asian, 121-126, 2015 | 6 | 2015 |
| Reliable test architecture with test cost reduction for systolic based DNN accelerators M Ibtesam, US Solangi, J Kim, MA Ansari, S Park IEEE Transactions on Circuits and Systems II: Express Briefs, 2021 | 5 | 2021 |
| Efficient diagnosis technique for aging defects on automotive semiconductor chips J Jung, MA Ansari, D Kim, H Yi, S Park Test Symposium (ETS), 2015 20th IEEE European, 1-2, 2015 | 2 | 2015 |
| Time Division Multiplexing based Test Access for Stacked ICs MA Ansari, US Solnagi, J Kim, AM Bughio, S Park JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 19 (1), 87-96, 2019 | 1 | 2019 |
| Enabling test/diagnosis of automotive semiconductor chips through FlexRay network MA Ansari, AR Ansari, J Kim, S Park Electrical and Computing Technologies and Applications (ICECTA), 2017 …, 2017 | 1 | 2017 |
| Low Power Scan Chain Reordering Method with Limited Routing Congestion for Code-based Test Data Compression D Kim, MA Ansari, J Jung, S Park JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 16 (5), 582-594, 2016 | 1 | 2016 |
| Efficient Pre-Bond Testing of TSV Defects Based on IEEE std. 1500 Wrapper Cells J Jung, MA Ansari, D Kim, S Park JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 16 (2), 226-235, 2016 | 1 | 2016 |
| Two Tone Analysis of Magnesium Oxide Based Magnetic Tunnel Junctions AM Bughio, EA Buriro, MA Ansari, N Nizamani, SH Siyal Quaid-E-Awam University Research Journal of Engineering, Science …, 2020 | | 2020 |
| Study on Early Capture Based VLSI Aging Monitoring Techniques I Sario, AB Channa, FA Qureshi, AM Kamboh, RK Nangdev, MA Ansari 2019 2nd International Conference on Computing, Mathematics and Engineering …, 2019 | | 2019 |
| Time-Multiplexed-Network for Test Cost Reduction (vol 37, pg 1681, 2018) MA Ansari, J Jung, D Kim, S Park IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND …, 2018 | | 2018 |
| Erratum to “Time-Multiplexed-Network for Test Cost Reduction” MA Ansari, J Jung, D Kim, S Park IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | | 2018 |
| Network Load Analysis During Test Mode for the Network-on-Chip Reused Test Access Mechanisms MA Ansari 2018 International Conference on Computing, Electronics & Communications …, 2018 | | 2018 |
Dr. Umair Saeed SolangiAssistant Professor, Quaid-e-Awam University of Engineering, Science & Technology, PakistanVerifierad e-postadress på quest.edu.pk
