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Zachery A. Jacobson
Zachery A. Jacobson
Head of Central Strategy and Insights, Google
Verified email at google.com - Homepage
Title
Cited by
Cited by
Year
Wafer-scale assembly of highly ordered semiconductor nanowire arrays by contact printing
Z Fan, JC Ho, ZA Jacobson, R Yerushalmi, RL Alley, H Razavi, A Javey
Nano letters 8 (1), 20-25, 2008
6662008
Controlled nanoscale doping of semiconductors via molecular monolayers
JC Ho, R Yerushalmi, ZA Jacobson, Z Fan, RL Alley, A Javey
Nature materials 7 (1), 62-67, 2008
3762008
Large-scale, heterogeneous integration of nanowire arrays for image sensor circuitry
Z Fan, JC Ho, ZA Jacobson, H Razavi, A Javey
Proceedings of the National Academy of Sciences 105 (32), 11066-11070, 2008
2982008
Large scale, highly ordered assembly of nanowire parallel arrays by differential roll printing
R Yerushalmi, ZA Jacobson, JC Ho, Z Fan, A Javey
Applied Physics Letters 91 (20), 203104, 2007
1622007
Tunnel field effect transistor with raised germanium source
SH Kim, S Agarwal, ZA Jacobson, P Matheu, C Hu, TJK Liu
IEEE Electron Device Letters 31 (10), 1107-1109, 2010
1492010
Formation and Characterization of Ni x InAs/InAs Nanowire Heterostructures by Solid Source Reaction
YL Chueh, AC Ford, JC Ho, ZA Jacobson, Z Fan, CY Chen, LJ Chou, ...
Nano letters 8 (12), 4528-4533, 2008
792008
Impact of body doping and thickness on the performance of Germanium-source TFETs
SH Kim, ZA Jacobson, TJK Liu
IEEE Transactions on Electron Devices 57 (7), 1710-1713, 2010
342010
Generic nanomaterial positioning by carrier and stationary phase design
R Yerushalmi, JC Ho, ZA Jacobson, A Javey
Nano letters 7 (9), 2764-2768, 2007
262007
Capacitive transducer strengthening via ALD-enabled partial gap filling
LW Hung, ZA Jacobson, Z Ren, A Javey, CTC Nguyen
Proc. Solid State Sens., Actuators, Microsyst. Workshop Tech. Dig, 1–5, 2008
192008
Planar GeOI TFET Performance Improvement With Back Biasing
P Matheu, B Ho, ZA Jacobson, TJK Liu
Electron Devices, IEEE Transactions on 59 (6), 1629-1635, 2012
162012
Tunnel FET-based pass-transistor logic for ultra-low-power applications
SH Kim, ZA Jacobson, P Patel, C Hu, TJK Liu
69th Device Research Conference, 133-134, 2011
72011
Improving the semiconductor industry through advanced analytics
G Batra, Z Jacobson, N Santhanam
McKinsey on Semiconductors, 2016
52016
Raised-Source/Drain Double-Gate Transistor Design Optimization for Low Operating Power
D Chen, ZA Jacobson, TJK Liu
IEEE Transactions on Electron Devices 60 (3), 1040-1045, 2013
32013
Band-to-Band Tunneling Transistors: Scalability and Circuit Performance
ZA Jacobson
CALIFORNIA UNIV BERKELEY DEPT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE, 2013
22013
Steep-subthreshold-slope devices on SOI
TJK Liu, P Matheu, Z Jacobson, SH Kim
IEEE 2011 International SOI Conference, 1-2, 2011
22011
3 Benchmarking alternative device structures for the terascale regime
ZA Jacobson, KJ Kuhn
CMOS and Beyond: Logic Switches for Terascale Integrated Circuits, 39, 2015
2015
2 Beyond transistor scaling: alternative device structures for the terascale regime
ZA Jacobson, KJ Kuhn
CMOS and Beyond: Logic Switches for Terascale Integrated Circuits, 14, 2015
2015
(Thomas D. Callinan Award of the Dielectric Science and Technology Division) Ge-Source TFETs for Ultra-Low-Power Electronics
TJK Liu, SH Kim, Z Jacobson
ECS, 2011
2011
2D and 3D integration of nanowires for flexible electronics
Z Fan, JC Ho, ZA Jacobson, H Razavi, R Yerushalmi, JW Do, A Moriwaki, ...
Materials Research Society Spring Meeting, 2009
2009
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Articles 1–19