| Reducing clock skew variability via cross links A Rajaram, J Hu, R Mahapatra Proceedings of the 41st annual Design Automation Conference, 18-23, 2004 | 139 | 2004 |
| Practical techniques to reduce skew and its variations in buffered clock networks G Venkataraman, N Jayakumar, J Hu, P Li, S Khatri, A Rajaram, ... ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005 …, 2005 | 70 | 2005 |
| MeshWorks: An efficient framework for planning, synthesis and optimization of clock mesh networks A Rajaram, DZ Pan 2008 Asia and South Pacific Design Automation Conference, 250-257, 2008 | 68 | 2008 |
| Variation tolerant buffered clock network synthesis with cross links A Rajaram, DZ Pan Proceedings of the 2006 international symposium on Physical design, 157-164, 2006 | 67 | 2006 |
| Improved algorithms for link-based non-tree clock networks for skew variability reduction A Rajaram, DZ Pan, J Hu Proceedings of the 2005 international symposium on Physical design, 55-62, 2005 | 41 | 2005 |
| Analysis and optimization of NBTI induced clock skew in gated clock trees A Chakraborty, G Ganesan, A Rajaram, DZ Pan 2009 Design, Automation & Test in Europe Conference & Exhibition, 296-299, 2009 | 35 | 2009 |
| A 65nm C64x+ multi-core DSP platform for communications infrastructure S Agarwala, A Rajagopal, A Hill, M Joshi, S Mullinnix, T Anderson, ... 2007 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2007 | 35 | 2007 |
| MeshWorks: A comprehensive framework for optimized clock mesh network synthesis A Rajaram, DZ Pan IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010 | 34 | 2010 |
| Design for manufacturing meets advanced process control: A survey DZ Pan, P Yu, M Cho, A Ramalingam, K Kim, A Rajaram, SX Shi Journal of Process Control 18 (10), 975-984, 2008 | 34 | 2008 |
| Robust chip-level clock tree synthesis A Rajaram, DZ Pan IEEE transactions on computer-aided design of integrated circuits and …, 2011 | 31 | 2011 |
| Robust chip-level clock tree synthesis for SOC designs A Rajaram, DZ Pan Proceedings of the 45th annual Design Automation Conference, 720-723, 2008 | 21 | 2008 |
| Fast incremental link insertion in clock networks for skew variability reduction A Rajaram, DZ Pan 7th International Symposium on Quality Electronic Design (ISQED'06), 6 pp.-84, 2006 | 17 | 2006 |
| Sensitivity based link insertion for variation tolerant clock network synthesis JS Yang, A Rajaram, N Shi, J Chen, DZ Pan 8th International Symposium on Quality Electronic Design (ISQED'07), 398-403, 2007 | 9 | 2007 |
| Context analysis and validation of lithography induced systematic variations in 65nm designs A Rajagopal, A Rajaram, R Damodaran, F Cano, S Swaminathan, ... Design for Manufacturability through Design-Process Integration II 6925, 77-84, 2008 | 6 | 2008 |
| Bufformer: A generative ml framework for scalable buffering R Liang, S Nath, A Rajaram, J Hu, H Ren Proceedings of the 28th Asia and South Pacific Design Automation Conference …, 2023 | 5 | 2023 |
| Automatic synthesis of complex clock systems T Lin, J Long, A Rajaram, M Bezman US Patent 9,058,451, 2015 | 5 | 2015 |
| Analytical bound for unwanted clock skew due to wire width variation A Rajaram, B Lu, J Hu, R Mahapatra, W Guo IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006 | 5 | 2006 |
| Practical clock tree robustness signoff metrics A Rajaram, R Damodaran, A Rajagopal 9th International Symposium on Quality Electronic Design (isqed 2008), 676-679, 2008 | 4 | 2008 |
| Clock tree synthesis based on computing critical clock latency probabilities AK Rajaram, A Cao US Patent 10,073,944, 2018 | 2 | 2018 |
| Clock network power estimation for logical designs M Pan, F Sheng, AK Rajaram US Patent 11,526,642, 2022 | | 2022 |
David Z. PanProfessor, Silicon Labs Endowed Chair, ECE Dept., University of Texas at AustinVerifierad e-postadress på ece.utexas.edu
