| Reli: Hardware/software checkpoint and recovery scheme for embedded processors T Li, R Ragel, S Parameswaran 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 875-880, 2012 | 39 | 2012 |
| Processor design for soft errors: Challenges and state of the art T Li, JA Ambrose, R Ragel, S Parameswaran ACM Computing Surveys (CSUR) 49 (3), 1-44, 2016 | 34 | 2016 |
| RASTER: Runtime adaptive spatial/temporal error resiliency for embedded processors T Li, M Shafique, JA Ambrose, S Rehman, J Henkel, S Parameswaran Proceedings of the 50th Annual Design Automation Conference, 1-7, 2013 | 28 | 2013 |
| DHASER: dynamic heterogeneous adaptation for soft-error resiliency in ASIP-based multi-core systems T Li, M Shafique, S Rehman, JA Ambrose, J Henkel, S Parameswaran 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 646-653, 2013 | 20 | 2013 |
| Overview and investigation of SEU detection and recovery approaches for FPGA-based heterogeneous systems E Cetin, O Diessel, T Li, JA Ambrose, T Fisk, S Parameswaran, ... FPGAs and Parallel Architectures for Aerospace Applications: Soft Errors and …, 2016 | 19 | 2016 |
| Side channel attacks in embedded systems: A tale of hostilities and deterrence JA Ambrose, RG Ragel, D Jayasinghe, T Li, S Parameswaran Sixteenth International Symposium on Quality Electronic Design, 452-459, 2015 | 19 | 2015 |
| CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors T Li, M Shafique, S Rehman, S Radhakrishnan, R Ragel, JA Ambrose, ... 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 707-712, 2013 | 13 | 2013 |
| Fine-grained checkpoint recovery for application-specific instruction-set processors T Li, M Shafique, JA Ambrose, J Henkel, S Parameswaran IEEE Transactions on Computers 66 (4), 647-660, 2016 | 12 | 2016 |
| RECORD: Reducing register traffic for checkpointing in embedded processors T Li, JA Ambrose, S Parameswaran 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 582-587, 2016 | 9 | 2016 |
| Hardware trojan mitigation in pipelined mpsocs A Malekpour, R Ragel, T Li, H Javaid, A Ignjatovic, S Parameswaran ACM Transactions on Design Automation of Electronic Systems (TODAES) 25 (1 …, 2020 | 7 | 2020 |
| FaSe: fast selective flushing to mitigate contention-based cache timing attacks T Li, S Parameswaran Proceedings of the 59th ACM/IEEE Design Automation Conference, 541-546, 2022 | 6 | 2022 |
| Argus: A framework for rapid design and prototype of heterogeneous multicore systems in fpga JA Ambrose, T Li, D Murphy, S Gargg, N Higgins, S Parameswaran 2015 28th International Conference on VLSI Design, 29-34, 2015 | 6 | 2015 |
| Scalable performance monitoring of application specific multiprocessor Systems-on-Chip JA Ambrose, V Cassisi, D Murphy, T Li, D Jayasinghe, S Parameswaran 2013 IEEE 8th International Conference on Industrial and Information Systems …, 2013 | 6 | 2013 |
| 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE) T Li, JA Ambrose, S Parameswaran Design Automation & Test in Europe Conference & Exhibition (DATE), 880-883, 2015 | 4 | 2015 |
| SIMF: Single-instruction multiple-flush mechanism for processor temporal isolation T Li, B Hopkins, S Parameswaran arXiv preprint arXiv:2011.10249, 2020 | 3 | 2020 |
| SHORE: hardware/software method for memory safety acceleration on RISC-V HK Dow, T Li, W Miles, S Parameswaran 2021 58th ACM/IEEE Design Automation Conference (DAC), 289-294, 2021 | 2 | 2021 |
| COPS: A complete oblivious processing system S Hussain, H Guo, T Li, H Saadat, S Parameswaran Microprocessors and Microsystems 85, 104295, 2021 | 2 | 2021 |
| A sub-range error characterization based selection methodology for approximate arithmetic units H Saadat, T Li, H Javaid, S Parameswaran 2020 33rd International Conference on VLSI Design and 2020 19th …, 2020 | 2 | 2020 |
| Fine-grained hardware/software methodology for process migration in MPSoCs T Li, JA Ambrose, S Parameswaran Proceedings of the International Conference on Computer-Aided Design, 508-515, 2012 | 2 | 2012 |
| HWST128: complete memory safety accelerator on RISC-V with metadata compression HK Dow, T Li, S Parameswaran Proceedings of the 59th ACM/IEEE Design Automation Conference, 709-714, 2022 | 1 | 2022 |
Jude Angelo AmbrosePostdoctoral Research Associate of School of Computer Science and Engineering, University of New South Wales, AustraliaVerifierad e-postadress på cse.unsw.edu.au
