Deog-Kyoon Jeong
Deog-Kyoon Jeong
Seoul National University, Department of Electrical and Computer Engineering
Verified email at - Homepage
Cited by
Cited by
An efficient charge recovery logic circuit
Y Moon, DK Jeong
IEEE Journal of Solid-State Circuits 31 (4), 514-522, 1996
An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance
Y Moon, J Choi, K Lee, DK Jeong, MK Kim
IEEE Journal of Solid-State Circuits 35 (3), 377-384, 2000
System and method for sending multiple data signals over a serial link
S Kim, DD Lee, DK Jeong
US Patent 5,835,498, 1998
Design of PLL-based clock generation circuits
DK Jeong, G Borriello, DA Hodges, RH Katz
IEEE Journal of Solid-State Circuits 22 (2), 255-261, 1987
A 0.18-μm CMOS 3.5-Gb/s continuous-time adaptive cable equalizer using enhanced low-frequency gain control method
JS Choi, MS Hwang, DK Jeong
IEEE Journal of Solid-State Circuits 39 (3), 419-425, 2004
A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL
S Kim, K Lee, Y Moon, DK Jeong, Y Choi, HK Lim
IEEE Journal of Solid-state circuits 32 (5), 691-700, 1997
A^ 3: Accelerating attention mechanisms in neural networks with approximation
TJ Ham, SJ Jung, S Kim, YH Oh, Y Park, Y Song, JH Park, S Lee, K Park, ...
2020 IEEE International Symposium on High Performance Computer Architecture …, 2020
A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS-and cellular-CDMA wireless systems
Y Koo, H Huh, Y Cho, J Lee, J Park, K Lee, DK Jeong, W Kim
IEEE Journal of solid-state circuits 37 (5), 536-542, 2002
A CMOS serial link for fully duplexed data communication
K Lee, S Kim, G Ahn, DK Jeong
IEEE Journal of Solid-State Circuits 30 (4), 353-364, 1995
Reduction of pump current mismatch in charge-pump PLL
MS Hwang, J Kim, DK Jeong
Electronics letters 45 (3), 135-136, 2009
Full-CMOS 2-GHz WCDMA direct conversion transmitter and receiver
KY Lee, SW Lee, Y Koo, HK Huh, HY Nam, JW Lee, J Park, K Lee, ...
IEEE Journal of Solid-State Circuits 38 (1), 43-53, 2003
A low-jitter 5000ppm spread spectrum clock generator for multi-channel SATA transceiver in 0.18/spl mu/m CMOS
HR Lee, O Kim, G Ahn, DK Jeong
ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State …, 2005
High speed serial link for fully duplexed data communication
DK Jeong
US Patent 5,675,584, 1997
A practical implementation of IEEE 1588-2008 transparent clock for distributed measurement and control systems
J Han, DK Jeong
IEEE transactions on instrumentation and measurement 59 (2), 433-439, 2009
Multi-gigabit-rate clock and data recovery based on blind oversampling
J Kim, DK Jeong
IEEE Communications Magazine 41 (12), 68-74, 2003
Single chip CMOS transmitter/receiver and method of using same
K Lee, DK Jeong, J Park, W Kim
US Patent 6,781,424, 2004
A 20-GHz phase-locked loop for 40-Gb/s serializing transmitter in 0.13-μm CMOS
J Kim, JK Kim, BJ Lee, N Kim, DK Jeong, W Kim
IEEE Journal of Solid-State Circuits 41 (4), 899-908, 2006
A 5-Gb/s 0.25-μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit
SH Lee, MS Hwang, Y Choi, S Kim, Y Moon, BJ Lee, DK Jeong, W Kim, ...
IEEE Journal of Solid-State Circuits 37 (12), 1822-1830, 2002
Multisection memory bank system
D Lee, Y Shin, DD Lee, DK Jeong, S Kong
US Patent 7,340,558, 2008
A single-inductor, multiple-channel current-balancing LED driver for display backlight applications
HC Kim, CS Yoon, DK Jeong, J Kim
IEEE Transactions on Industry Applications 50 (6), 4077-4081, 2014
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