Saurabh Sant
Saurabh Sant
Verified email at ethz.ch
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Year
Individual defects in InAs/InGaAsSb/GaSb nanowire tunnel field-effect transistors operating below 60 mV/decade
E Memisevic, M Hellenbrand, E Lind, AR Persson, S Sant, A Schenk, ...
Nano letters 17 (7), 4373-4380, 2017
572017
Lateral InAs/Si p-type tunnel FETs integrated on Si—Part 2: Simulation study of the impact of interface traps
S Sant, K Moselund, D Cutaia, H Schmid, M Borg, H Riel, A Schenk
IEEE Transactions on Electron Devices 63 (11), 4240-4247, 2016
492016
Band-offset engineering for GeSn-SiGeSn hetero tunnel FETs and the role of strain
S Sant, A Schenk
IEEE Journal of the Electron Devices Society 3 (3), 164-175, 2015
452015
Methods to enhance the performance of InGaAs/InP heterojunction tunnel FETs
S Sant, A Schenk
IEEE Transactions on Electron Devices 63 (5), 2169-2175, 2015
422015
Band gap bowing and band offsets in relaxed and strained Si1xGex alloys by employing a new nonlinear interpolation scheme
S Sant, S Lodha, U Ganguly, S Mahapatra, FO Heinz, L Smith, V Moroz, ...
Journal of Applied Physics 113 (3), 033708, 2013
372013
Pseudopotential calculations of strained-GeSn/SiGeSn hetero-structures
S Sant, A Schenk
Applied Physics Letters 105 (16), 162101, 2014
322014
Lateral InAs/Si p-type tunnel FETs integrated on Si—part 1: experimental devices
KE Moselund, D Cutaia, H Schmid, M Borg, S Sant, A Schenk, H Riel
IEEE Transactions on Electron Devices 63 (11), 4233-4239, 2016
262016
The effect of density-of-state tails on band-to-band tunneling: Theory and application to tunnel field effect transistors
S Sant, A Schenk
Journal of Applied Physics 122 (13), 135702, 2017
172017
III–V-based hetero tunnel FETs: A simulation study with focus on non-ideality effects
A Schenk, S Sant, K Moselund, H Riel
2016 Joint International EUROSOI Workshop and International Conference on …, 2016
162016
Manipulating surface states of III–V nanowires with uniaxial stress
G Signorello, S Sant, N Bologna, M Schraff, U Drechsler, H Schmid, ...
Nano letters 17 (5), 2816-2824, 2017
152017
A scaled replacement metal gate InGaAs-on-Insulator n-FinFET on Si with record performance
H Hahn, V Deshpande, E Caruso, S Sant, E O'Connor, Y Baumgartner, ...
2017 IEEE International Electron Devices Meeting (IEDM), 17.5. 1-17.5. 4, 2017
142017
Impact of trap-assisted tunneling and channel quantization on InAs/Si hetero tunnel FETs
S Sant, A Schenk, K Moselund, H Riel
2016 74th Annual Device Research Conference (DRC), 1-2, 2016
132016
InGaAs-on-insulator FinFETs with reduced off-current and record performance
C Convertino, C Zota, S Sant, F Eltes, M Sousa, D Caimi, A Schenk, ...
2018 IEEE International Electron Devices Meeting (IEDM), 39.2. 1-39.2. 4, 2018
102018
Facet-selective group-III incorporation in InGaAs template assisted selective epitaxy
M Borg, L Gignac, J Bruley, A Malmgren, S Sant, C Convertino, ...
Nanotechnology 30 (8), 084004, 2018
92018
Impact of Floating Body Effect, Back-Gate Traps, and Trap-Assisted Tunneling on Scaled In0.53Ga0.47As Ultrathin-Body MOSFETs and Mitigation Measures
S Sant, P Aguirre, H Hahn, V Deshpande, L Czornomaz, A Schenk
IEEE Transactions on Electron Devices 65 (6), 2578-2584, 2018
72018
The impact of hetero-junction and oxide-interface traps on the performance of InAs/Si tunnel FETs
A Schenk, S Sant, K Moselund, H Riel
2017 17th International Workshop on Junction Technology (IWJT), 27-30, 2017
72017
Complementary III–V heterostructure tunnel FETs
KE Moselund, D Cutaia, H Schmid, H Riel, S Sant, A Schenk
2016 46th European Solid-State Device Research Conference (ESSDERC), 403-407, 2016
72016
comparative simulation study of InAs/Si and All-III-V hetero tunnel FETs
A Schenk, S Sant, K Moselund, H Riel
ECS Transactions 66 (5), 157, 2015
62015
Analysis of GeSn-SiGeSn hetero-tunnel FETs
S Sant, QT Zhao, D Buca, S Mantl, A Schenk
2014 International Conference on Simulation of Semiconductor Processes and …, 2014
62014
The impact of hetero-junction and oxide-interface traps on the performance of InAs/Si and InAs/GaAsSb nanowire tunnel FETs
A Schenk, S Sant, K Moselund, H Riel, E Memisevic, LE Wernersson
2017 International Conference on Simulation of Semiconductor Processes and …, 2017
52017
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