| The CHERI capability model: Revisiting RISC in an age of risk J Woodruff, RNM Watson, D Chisnall, SW Moore, J Anderson, B Davis, ... ACM SIGARCH Computer Architecture News 42 (3), 457-468, 2014 | 437 | 2014 |
| CHERI: A hybrid capability-system architecture for scalable software compartmentalization RNM Watson, J Woodruff, PG Neumann, SW Moore, J Anderson, ... 2015 IEEE Symposium on Security and Privacy, 20-37, 2015 | 395 | 2015 |
| Capability hardware enhanced RISC instructions: CHERI instruction-set architecture (version 7) RNM Watson, PG Neumann, J Woodruff, M Roe, H Almatary, J Anderson, ... University of Cambridge, Computer Laboratory, 2019 | 136 | 2019 |
| Beyond the PDP-11: Architectural support for a memory-safe C abstract machine D Chisnall, C Rothwell, RNM Watson, J Woodruff, M Vadera, SW Moore, ... ACM SIGARCH Computer Architecture News 43 (1), 117-130, 2015 | 116 | 2015 |
| CheriABI: Enforcing valid pointer provenance and minimizing pointer privilege in the POSIX C run-time environment B Davis, RNM Watson, A Richardson, PG Neumann, SW Moore, ... Proceedings of the Twenty-Fourth International Conference on Architectural …, 2019 | 93 | 2019 |
| Cherivoke: Characterising pointer revocation using cheri capabilities for temporal memory safety H Xia, J Woodruff, S Ainsworth, NW Filardo, M Roe, A Richardson, ... Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019 | 85 | 2019 |
| Cornucopia: Temporal safety for CHERI heaps NW Filardo, BF Gutstein, J Woodruff, S Ainsworth, L Paul-Trifu, B Davis, ... 2020 IEEE Symposium on Security and Privacy (SP), 608-625, 2020 | 82 | 2020 |
| Efficient tagged memory A Joannou, J Woodruff, R Kovacsics, SW Moore, A Bradbury, H Xia, ... 2017 IEEE International Conference on Computer Design (ICCD), 641-648, 2017 | 81 | 2017 |
| Cheri concentrate: Practical compressed capabilities J Woodruff, A Joannou, H Xia, A Fox, RM Norton, D Chisnall, B Davis, ... IEEE Transactions on Computers 68 (10), 1455-1469, 2019 | 77 | 2019 |
| Fast protection-domain crossing in the CHERI capability-system architecture RNM Watson, RM Norton, J Woodruff, SW Moore, PG Neumann, ... IEEE Micro 36 (5), 38-49, 2016 | 58 | 2016 |
| CHERI JNI: Sinking the Java security model into the C D Chisnall, B Davis, K Gudka, D Brazdil, A Joannou, J Woodruff, ... ACM SIGARCH Computer Architecture News 45 (1), 569-583, 2017 | 51 | 2017 |
| The CHERI capability model: Revisiting RISC in an age of risk. In 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA) J Woodruff, RNM Watson, D Chisnall, SW Moore, J Anderson, B Davis, ... IEEE. doi 10, 2014 | 37 | 2014 |
| Capability hardware enhanced RISC instructions: CHERI instruction-set architecture RNM Watson, PG Neumann, J Woodruff, M Roe, J Anderson, D Chisnall, ... University of Cambridge, Computer Laboratory, 2015 | 34 | 2015 |
| Cheri: a research platform deconflating hardware virtualisation and protection RNM Watson, PG Neumann, J Woodruff, J Anderson, R Anderson, ... Runtime Environments, Systems, Layering and Virtualized Environments (RESoLVE), 2012 | 32 | 2012 |
| Cherirtos: A capability model for embedded devices H Xia, J Woodruff, H Barral, L Esswood, A Joannou, R Kovacsics, ... 2018 IEEE 36th International Conference on Computer Design (ICCD), 92-99, 2018 | 31 | 2018 |
| Capability hardware enhanced RISC instructions (CHERI): Notes on the Meltdown and Spectre attacks RNM Watson, J Woodruff, M Roe, SW Moore, PG Neumann University of Cambridge, Computer Laboratory, 2018 | 29 | 2018 |
| CHERI: A RISC capability machine for practical memory safety JD Woodruff University of Cambridge, Computer Laboratory, 2014 | 27 | 2014 |
| The arm morello evaluation platform—validating cheri-based security in a high-performance system R Grisenthwaite, G Barnes, RNM Watson, SW Moore, P Sewell, ... IEEE Micro 43 (3), 50-57, 2023 | 18 | 2023 |
| Bluespec Extensible RISC Implementation: BERI Hardware reference RNM Watson, J Woodruff, D Chisnall, B Davis, W Koszek, AT Markettos, ... University of Cambridge, Computer Laboratory, 2015 | 16 | 2015 |
| Capability Hardware Enhanced RISC Instructions: CHERI Programmer’s Guide RNM Watson, D Chisnall, B Davis, W Koszek, SW Moore, SJ Murdoch, ... University of Cambridge, Computer Laboratory, 2015 | 12 | 2015 |
Simon MooreProfessor of Computer Engineering, University of CambridgeVerifierad e-postadress på cl.cam.ac.uk
