| Fast analog layout prototyping for nanometer design migration YP Weng, HM Chen, TC Chen, PC Pan, CH Chen, WZ Chen 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 517-522, 2011 | 43 | 2011 |
| Configurable analog routing methodology via technology and design constraint unification PC Pan, HM Chen, YK Cheng, J Liu, WY Hu Proceedings of the International Conference on Computer-Aided Design, 620-626, 2012 | 27 | 2012 |
| Integrated hierarchical synthesis of analog/RF circuits with accurate performance mapping KH Meng, PC Pan, HM Chen 2011 12th International Symposium on Quality Electronic Design, 1-8, 2011 | 26 | 2011 |
| A fast prototyping framework for analog layout migration with planar preservation PC Pan, CY Chin, HM Chen, TC Chen, CC Lee, JC Lin IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015 | 23 | 2015 |
| Analog placement with current flow and symmetry constraints using pcp-sp A Patyal, PC Pan, HM Chen, HY Chi, CN Liu Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018 | 21 | 2018 |
| Efficient analog layout prototyping by layout reuse with routing preservation CY Chin, PC Pan, HM Chen, TC Chen, JC Lin 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 40-47, 2013 | 16 | 2013 |
| PAGE: parallel agile genetic exploration towards utmost performance for analog circuit design. PC Pan, HM Chen, CC Lin DATE, 1849-1854, 2013 | 14 | 2013 |
| An efficient learning-based approach for performance exploration on analog and RF circuit synthesis PC Pan, CC Huang, HM Chen Proceedings of the 56th Annual Design Automation Conference 2019, 1-2, 2019 | 13 | 2019 |
| Efficient analog layout prototyping by layout reuse with routing preservation TC Chen, PC Pan, CY Chin, HM Chen US Patent 10,409,943, 2019 | 9 | 2019 |
| Exploring multiple analog placements with partial-monotonic current paths and symmetry constraints using PCP-SP A Patyal, PC Pan, KA Asha, HM Chen, WZ Chen IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020 | 4 | 2020 |
| Method for layout generation with constrained hypergraph partitioning Y Tsun-Yu, WY Hu, JF Kuan, HS Lee, PC Pan, HW Huang, HM Chen, ... US Patent 10,509,883, 2019 | 2 | 2019 |
| On Closing the Gap Between Pre-Simulation and Post-Simulation Results in Nanometer Analog Layouts PC Pan, HW Huang, CC Huang, A Patyal, HM Chen, TY Yang 2018 15th International Conference on Synthesis, Modeling, Analysis and …, 2018 | 2 | 2018 |
| An automatic synthesis tool for nanometer low dropout regulator using simulation based model and geometric programming SH Hsu, WZ Chen, JP Zheng, SSY Liu, PC Pan, HM Chen Technical Papers of 2014 International Symposium on VLSI Design, Automation …, 2014 | 1 | 2014 |
| 敏捷類比電路合成與佈局設計遷移方法 潘柏丞 國立交通大學, 2015 | | 2015 |
| A stochastic-based efficient critical area extractor on OpenAccess platform BZ Chen, HM Chen, LD Huang, PC Pan Proceedings of the 19th ACM Great Lakes symposium on VLSI, 197-202, 2009 | | 2009 |
| A Fast Prototyping Methodology with Constrained Floorplaning on Analog Layout Generation PC Pan, HM Chen, HW Huang | | |
| An Automated Flow Integration to Help Analog Layout Design Migration JC Lin, PC Pan, CY Chin, HM Chen | | |
| An Agile Migration Framework for Analog Layout Design PC Pan, HM Chen | | |
Hung-Ming ChenNational Chiao Tung UniversityVerifierad e-postadress på g2.nctu.edu.tw
