Kirsten Moselund
Kirsten Moselund
IBM Research
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Template-assisted selective epitaxy of III–V nanoscale devices for co-planar heterogeneous integration with Si
H Schmid, M Borg, K Moselund, L Gignac, CM Breslin, J Bruley, D Cutaia, ...
Applied Physics Letters 106 (23), 233101, 2015
Vertical III–V nanowire device integration on Si (100)
M Borg, H Schmid, KE Moselund, G Signorello, L Gignac, J Bruley, ...
Nano letters 14 (4), 1914-1920, 2014
InAs–Si nanowire heterojunction tunnel FETs
KE Moselund, H Schmid, C Bessire, MT Bjork, H Ghoneim, H Riel
IEEE Electron Device Letters 33 (10), 1453-1455, 2012
Si–InAs heterojunction Esaki tunnel diodes with high current densities
MT Björk, H Schmid, CD Bessire, KE Moselund, H Ghoneim, S Karg, ...
Applied Physics Letters 97 (16), 163501, 2010
Fabrication and characterization of gate-all-around silicon nanowires on bulk silicon
V Pott, KE Moselund, D Bouvet, L De Michielis, AM Ionescu
IEEE transactions on nanotechnology 7 (6), 733-744, 2008
InAs-Si heterojunction nanowire tunnel diodes and tunnel FETs
H Riel, KE Moselund, C Bessire, MT Björk, A Schenk, H Ghoneim, ...
2012 International Electron Devices Meeting, 16.6. 1-16.6. 4, 2012
Silicon Nanowire Tunnel FETs: Low-Temperature Operation and Influence of High-Gate Dielectric
KE Moselund, MT Bjork, H Schmid, H Ghoneim, S Karg, E Lortscher, ...
IEEE transactions on electron devices 58 (9), 2911-2916, 2011
Lateral InAs/Si p-type tunnel FETs integrated on Si—Part 2: Simulation study of the impact of interface traps
S Sant, K Moselund, D Cutaia, H Schmid, M Borg, H Riel, A Schenk
IEEE Transactions on Electron Devices 63 (11), 4240-4247, 2016
Bended Gate-All-Around Nanowire MOSFET: a device with enhanced carrier mobility due to oxidation-induced tensile stress
KE Moselund, P Dobrosz, S Olsen, V Pott, L De Michielis, D Tsamados, ...
2007 IEEE International Electron Devices Meeting, 191-194, 2007
Mechanisms of template-assisted selective epitaxy of InAs nanowires on Si
M Borg, H Schmid, KE Moselund, D Cutaia, H Riel
Journal of Applied Physics 117 (14), 144303, 2015
High-mobility GaSb nanostructures cointegrated with InAs on Si
M Borg, H Schmid, J Gooth, MD Rossell, D Cutaia, M Knoedler, ...
ACS nano 11 (3), 2554-2560, 2017
The high-mobility bended n-channel silicon nanowire transistor
KE Moselund, M Najmzadeh, P Dobrosz, SH Olsen, D Bouvet, ...
IEEE transactions on electron devices 57 (4), 866-876, 2010
Comparison of VLS grown Si NW tunnel FETs with different gate stacks
KE Moselund, H Ghoneim, MT Bjork, H Schmid, S Karg, E Lortscher, ...
2009 Proceedings of the European Solid State Device Research Conference, 448-451, 2009
Complementary III–V heterojunction lateral NW tunnel FET technology on Si
D Cutaia, KE Moselund, H Schmid, M Borg, A Olziersky, H Riel
2016 IEEE Symposium on VlSI Technology, 1-2, 2016
Tunneling and occupancy probabilities: How do they affect tunnel-FET behavior?
L De Michielis, L Lattanzio, KE Moselund, H Riel, AM Ionescu
IEEE electron device letters 34 (6), 726-728, 2013
Room-temperature lasing from monolithically integrated GaAs microdisks on silicon
S Wirths, BF Mayer, H Schmid, M Sousa, J Gooth, H Riel, KE Moselund
ACS nano 12 (3), 2169-2175, 2018
Ballistic one-dimensional InAs nanowire cross-junction interconnects
J Gooth, M Borg, H Schmid, V Schaller, S Wirths, K Moselund, M Luisier, ...
Nano letters 17 (4), 2596-2602, 2017
Punch-through impact ionization MOSFET (PIMOS): From device principle to applications
KE Moselund, D Bouvet, V Pott, C Meinen, M Kayal, AM Ionescu
Solid-state electronics 52 (9), 1336-1344, 2008
Vertical InAs-Si gate-all-around tunnel FETs integrated on Si using selective epitaxy in nanotube templates
D Cutaia, KE Moselund, M Borg, H Schmid, L Gignac, CM Breslin, S Karg, ...
IEEE Journal of the Electron Devices Society 3 (3), 176-183, 2015
Fabrication of vertical InAs-Si heterojunction tunnel field effect transistors
H Schmid, KE Moselund, MT Björk, M Richter, H Ghoneim, CD Bessire, ...
69th Device Research Conference, 181-182, 2011
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