| Test architecture for systolic array of edge-based ai accelerator US Solangi, M Ibtesam, MA Ansari, J Kim, S Park IEEE Access 9, 96700-96710, 2021 | 14 | 2021 |
| Highly Efficient Test Architecture for Low-Power AI Accelerators M Ibtesam, US Solangi, J Kim, MA Ansari, S Park IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021 | 12 | 2021 |
| Reliable Test Architecture With Test Cost Reduction for Systolic-Based DNN Accelerators M Ibtesam, US Solangi, J Kim, MA Ansari, S Park IEEE Transactions on Circuits and Systems II: Express Briefs 69 (3), 1537-1541, 2021 | 5 | 2021 |
| CAN-Based aging monitoring technique for automotive ASICs with efficient soft error resilience J Kim, M Ibtesam, D Kim, J Jung, S Park IEEE Access 8, 22400-22410, 2020 | 3 | 2020 |
| Efficient low-power scan test method based on exclusive scan and scan chain reordering D Kim, J Kim, M Ibtesam, US Solangi, S Park Journal Of Semiconductor Technology and Science 20 (4), 390-404, 2020 | 2 | 2020 |
| Master-slave based test cost reduction method for DNN accelerators US Solangi, M Ibtesam, S Park IEICE Electronics Express 18 (24), 20210425-20210425, 2021 | 1 | 2021 |
| Time multiplexed LBIST for in-field testing of automotive AI accelerators US Solangi, M Ibtesam, S Park IEICE Electronics Express 18 (24), 20210451-20210451, 2021 | 1 | 2021 |
| Reliable Test Architecture for AI accelerators with test cost reduction M Ibtesam 한양대학교, 2022 | | 2022 |
Dr. Umair Saeed SolangiAssistant Professor, Quaid-e-Awam University of Engineering, Science & Technology, PakistanVerifierad e-postadress på quest.edu.pk
